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Coupling between 2D and Quantum Confinement Effects in Ultra-Short Channel Double-Gate MOSFETs 超短通道双栅mosfet中二维和量子约束效应的耦合
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195238
M. Mouis, A. Poncet
{"title":"Coupling between 2D and Quantum Confinement Effects in Ultra-Short Channel Double-Gate MOSFETs","authors":"M. Mouis, A. Poncet","doi":"10.1109/ESSDERC.2001.195238","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195238","url":null,"abstract":"This paper presents for the first time how quantum confinement effects are affected by gate shrinking in a double-gate MOS transistor. We clearly show how inter-gate distance and channel length are respectively impacting device parameters such as subthreshold slope, threshold voltage and maximum inversion charge. Leakage due to source-drain quantum coupling has been evidenced with the shortest gate lengths.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125747138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimized Si/SiGe notched gates for CMOS 优化CMOS的Si/SiGe陷波门
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195254
S. Monfray, C. Julien, P. Ribot, F. Boeuf, D. Dutartre, J. Martins, E. Søndergård, T. Skotnicki
{"title":"Optimized Si/SiGe notched gates for CMOS","authors":"S. Monfray, C. Julien, P. Ribot, F. Boeuf, D. Dutartre, J. Martins, E. Søndergård, T. Skotnicki","doi":"10.1109/ESSDERC.2001.195254","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195254","url":null,"abstract":"The process developed here uses the wellcontrolled and highly selective etching between Poly-SiGe and Poly-Si in a downstream plasma equipment for processing notched-gate devices. Two notch length, 15 and 30 nm, were processed. The optimum was clearly evidenced for the shortest notch (15 nm), in terms of performance and gate current reduction (at low field). For this notch length, no degradation in SCE and at the same time a slight improvement in Gmsat was measured in comparison with standard transistors. In addition, a reduction of poly-depletion due to a better activation of dopants in SiGe in both NMOS and PMOS gates has been measured.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125925373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Characterization and simulation of the parasitic BJT in 0.1um partially-depleted SOI devices 0.1um部分耗尽SOI器件中寄生BJT的表征与仿真
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195270
C. Fenouillet-Béranger, O. Faynot, J. de Pontcharra, C. Tabone, G. Lecarval, A. Grouillet, J. Pelloie, D. Balestra
{"title":"Characterization and simulation of the parasitic BJT in 0.1um partially-depleted SOI devices","authors":"C. Fenouillet-Béranger, O. Faynot, J. de Pontcharra, C. Tabone, G. Lecarval, A. Grouillet, J. Pelloie, D. Balestra","doi":"10.1109/ESSDERC.2001.195270","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195270","url":null,"abstract":"","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121395307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A New Model for Threshold Voltage Mismatch Based on the Random Fluctuations of Dopant Number in the MOS Transistor Gate 基于MOS晶体管栅极掺杂数随机波动的阈值电压失配新模型
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195260
R. Difrenza, P. Llinares, G. Morin, E. Granger, G. Ghibaudo
{"title":"A New Model for Threshold Voltage Mismatch Based on the Random Fluctuations of Dopant Number in the MOS Transistor Gate","authors":"R. Difrenza, P. Llinares, G. Morin, E. Granger, G. Ghibaudo","doi":"10.1109/ESSDERC.2001.195260","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195260","url":null,"abstract":"Matching characterization is an important element in analog applications as it allows taking into account the electrical differences that occur between identically designed devices in circuit design and simulation. Moreover, it is becoming more and more important in developing the future technologies as matching parameters can be considered as a factor of merit in term of process maturity and performance. In the case of MOS transistors, it has been widely reported that mismatch is related to the random fluctuations of channel dopant number [1] [2] [3]. Then, the model based on the statistical fluctuations of dopant in the channel region predicts an area scaling law for threshold voltage fluctuations given by:","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121462399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Advanced Source/Drain Architecture using Very Low Schottky Barriers: Device Design and Material Engineering 使用极低肖特基屏障的先进源/漏架构:设备设计和材料工程
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195236
E. Dubois, G. Larrieu
{"title":"Advanced Source/Drain Architecture using Very Low Schottky Barriers: Device Design and Material Engineering","authors":"E. Dubois, G. Larrieu","doi":"10.1109/ESSDERC.2001.195236","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195236","url":null,"abstract":"The Accumulation Low Schottky Barrier MOSFET (ALSB-SOI-MOS) is shown to provide a pragmatic solution to the aforementioned limitations: the junction depth issue is inherently removed as Schottky contacts do not require doped source/drain extensions silicide penetration and silicon consumption is not limited and can even provide enhanced performances material engineering provides extremely low Schottky barriers high channel doping and related effects (dopant f luctuation, hot carriers) are minimized.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134428661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
92-GHz-Dynamic and 72-GHz-Static Frequency Dividers Using 5.4-ps-ECL Self-Aligned SEG SiGe HBTs 使用5.4 ps ecl自对准SEG SiGe hbt的92 ghz动态和72 ghz静态分频器
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195295
K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto
{"title":"92-GHz-Dynamic and 72-GHz-Static Frequency Dividers Using 5.4-ps-ECL Self-Aligned SEG SiGe HBTs","authors":"K. Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto","doi":"10.1109/ESSDERC.2001.195295","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195295","url":null,"abstract":"A dynamic frequency divider with a maximum operating frequency of up to 92 GHz and a static frequency divider with a maximum operating frequency of up to 72 GHz were developed for future millimeter-wave communication systems. These frequency dividers were fabricated by using self-aligned selective-epitaxial-growth (SEG) SiGe heterojunction bipolar transistors (HBTs). By applying a high-boron-doping base and optimizing the thickness of the Si-cap layer, a 130-GHz cutoff frequency and an ECL gate delay time of 5.4 ps were achieved for these SiGe HBTs.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134056248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Behaviour of the CoolMOS device and its body diode CoolMOS器件及其主体二极管的性能
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195248
K. Sheng, F. Udrea, G. Amaratunga, P. Palmer
{"title":"Behaviour of the CoolMOS device and its body diode","authors":"K. Sheng, F. Udrea, G. Amaratunga, P. Palmer","doi":"10.1109/ESSDERC.2001.195248","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195248","url":null,"abstract":"The behaviour of the CoolMOS and its internal body-drain diode has been studied in experiments and found to show significant differences to a conventional power MOSFET. The device demonstrated significant superiority over the conventional power MOSFET in on-state resistance and switching speed. Forward Biased SOA (FBSOA) of the CoolMOS device is found to exhibits unique characteristics. Reverse recovery behaviour of the body diode is found to be snappier than that of a traditional power MOSFET but less sensitive to the reverse blocking DC voltage. An equivalent power IGBT is also included for comparison. Physical explanations for these unique behaviours are explained and possible improvements investigated.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125179741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Evaluation of MOSFET Reliability in Analog Applications 模拟应用中MOSFET可靠性的评估
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195207
R. Thewes, R. Brederlow, C. Schlunder, P. Wieczorek, B. Ankele, A. Hesener, J. Holz, S. Kessel, W. Weber
{"title":"Evaluation of MOSFET Reliability in Analog Applications","authors":"R. Thewes, R. Brederlow, C. Schlunder, P. Wieczorek, B. Ankele, A. Hesener, J. Holz, S. Kessel, W. Weber","doi":"10.1109/ESSDERC.2001.195207","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195207","url":null,"abstract":"","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134181378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Optimization of Industrial High Voltage Structures by Three-Dimensional Diffusion Simulation 基于三维扩散模拟的工业高压结构优化
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195242
J. Červenka, P. Fleischmann, S. Selberherr, M. Knaipp, F. Unterleitner
{"title":"Optimization of Industrial High Voltage Structures by Three-Dimensional Diffusion Simulation","authors":"J. Červenka, P. Fleischmann, S. Selberherr, M. Knaipp, F. Unterleitner","doi":"10.1109/ESSDERC.2001.195242","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195242","url":null,"abstract":"A major goal in the process development of high voltage processes is the design of devices with given breakdown voltages and low switch on resistances. To reach this goal it is necessary to optimize the space charge regions of the device. Unfortunately these effects are three-dimensional and a device optimization needs the support of accurate three-dimensional simulation, which is shown in this article.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"505 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129117910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical Characterization of Memory-Cell Structures Employing Ultra-Thin Al2O3 Film as Storage Node 超薄Al2O3薄膜作为存储节点的记忆电池结构的电特性研究
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195220
A. Fernandes, B. De Salvo, P. Masson, G. Pananakakis, G. Ghibaudo, T. Baron, N. Buffet, D. Mariolle, B. Guillaumot
{"title":"Electrical Characterization of Memory-Cell Structures Employing Ultra-Thin Al2O3 Film as Storage Node","authors":"A. Fernandes, B. De Salvo, P. Masson, G. Pananakakis, G. Ghibaudo, T. Baron, N. Buffet, D. Mariolle, B. Guillaumot","doi":"10.1109/ESSDERC.2001.195220","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195220","url":null,"abstract":"Memory devices using ultra-thin (~1nm) layer of Al2O3 as storage medium have been fabricated and characterized. In this paper, conduction properties, write-erase and data retention characteristics are investigated. Moreover, a comparison with Si-dot floating gate memory devices is performed.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132410975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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