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A Procedure for Checking the Topological Consistency of A 2-D or 3-D Finite Element Mesh 检查二维或三维有限元网格拓扑一致性的步骤
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600108
K. Preiss
{"title":"A Procedure for Checking the Topological Consistency of A 2-D or 3-D Finite Element Mesh","authors":"K. Preiss","doi":"10.1109/DAC.1979.1600108","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600108","url":null,"abstract":"This paper describes procedures for checking the topological consistency of two- or three-dimensional finite element meshes. Two-dimensional meshes may include mixtures of triangles, quadrilaterals and other polygons, with optional side and center nodes. Three dimensional meshes may include tetrahedra and brick-shaped elements, with optional edge, face or center nodes.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115105837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SABLE: A Tool for Generating Structured, Multi-Level Simulations 生成结构化、多层次模拟的工具
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1145/62882.62925
D. Hill, W. M. V. Cleemput
{"title":"SABLE: A Tool for Generating Structured, Multi-Level Simulations","authors":"D. Hill, W. M. V. Cleemput","doi":"10.1145/62882.62925","DOIUrl":"https://doi.org/10.1145/62882.62925","url":null,"abstract":"SABLE (Structure And Behavior Linking Environment) is a system currently being developed at Stanford to support structured, multi-level behavior specification and simulation of digital systems. SABLE accepts information about the nesting and interconnectivity of components, and combines it with descriptions of their behavior, which are written in a new language called ADLIB (A Design Language for Indicating Behavior). ADLIB allows users to define the \"data level\" at which each component operates, and to specify mechanisms for translating information between these levels. The facilities provided by SABLE are general and flexible, making it feasible to simulate a large system at several levels of abstraction simultaneously. Examples are included that illustrate: the' use of ADLIB for behavior specification, techniques for data level translations, and a design methodology that makes use of multi-level simulation.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127229668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
PC Board Layout Techniques PC板布局技术
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600129
David R. Johnson
{"title":"PC Board Layout Techniques","authors":"David R. Johnson","doi":"10.1109/DAC.1979.1600129","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600129","url":null,"abstract":"This paper discusses general concepts and sample results of printed circuit board layout techniques involving the use of a general purpose, interactive graphics, computer aided design and manufacturing system. Employed is a balance of automatic processes and manual techniques proven to be effective for addressing a wide range of board sizes and types.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126290025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The Use of Color and 3-D Temporal and Spatial Data Management Techniques in Computer-Aided Design 彩色和三维时空数据管理技术在计算机辅助设计中的应用
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600085
Wayne E. Carlson, Richard E. Parent, C. Csuri
{"title":"The Use of Color and 3-D Temporal and Spatial Data Management Techniques in Computer-Aided Design","authors":"Wayne E. Carlson, Richard E. Parent, C. Csuri","doi":"10.1109/DAC.1979.1600085","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600085","url":null,"abstract":"An interactive system has been developed that facilitates closer interaction by a designer in the design process through the use of shaded color three-dimensional computer graphics to display appropriate design data. The use of traditional computer animation techniques allows for more efficient analysis of time dependent data, and advanced interactive methods of storing and retrieving spatial data offers help in displaying and evaluating the objects being designed. The system is planned to interface with an existing computer-aided design project that emphasizes the structural analysis phase of the design process. The fundamental goal of the project was to incorporate color graphics into the design system while maintaining a high degree of user interaction. Descriptions are included of the operating system environment and the necessary supporting software and hardware components. Modules of the display system are discussed and sample images are presented with examples of user interaction.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128443280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Behavioral-Level Test Development 行为水平测试开发
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600105
William A. Johnson
{"title":"Behavioral-Level Test Development","authors":"William A. Johnson","doi":"10.1109/DAC.1979.1600105","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600105","url":null,"abstract":"An argument is made that the economics of test development in the LSI-VLSI era require creation and use of test development software aids that operate from high-level behavioral circuit models. Behavioral models are defined to be abstract specifications of the circuit function. Problems with the use of current-day gate-level software aids are discussed. Suggestions are given for implementing behavioral-level test generation tools. Recent work in this area at Texas Instruments Incorporated (TI) is discussed.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121401970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Circuit Simulation and Timing Verification based on MOS/LSI Mask Information 基于MOS/LSI掩模信息的电路仿真与时序验证
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600093
T. Akino, M. Shimode, Yukinaga Kurashige, Toshio Negishi
{"title":"Circuit Simulation and Timing Verification based on MOS/LSI Mask Information","authors":"T. Akino, M. Shimode, Yukinaga Kurashige, Toshio Negishi","doi":"10.1109/DAC.1979.1600093","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600093","url":null,"abstract":"A mask analysis program for MOS/LSI mask layout data has been developed. This program converts all the mask layout data in one chip LSI into the corresponding circuit schema. A partitioning method for the large random logic circuit divides it into small subcircuits. It is shown that this method takes full advantage of the savings both in computer time and computer storage for the circuit simulation and timing verification of the random logic circuit having more than 500 active devices.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132389861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Descriptive Databases in Some Design/Manufacturing Environments 一些设计/制造环境中的描述性数据库
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600147
E. M. Hoskins
{"title":"Descriptive Databases in Some Design/Manufacturing Environments","authors":"E. M. Hoskins","doi":"10.1109/DAC.1979.1600147","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600147","url":null,"abstract":"In the development of substantial integrated computer-aided design systems, one of the most crucial features is the creation of purpose-made data structures. These have to be designed with growth and change in mind and in the course of the design process can reach a substantial size. They form the central source and design information about a particular product. They are used to generate drawings, assembly information schedules etc. for production purposes as well as being the data source and repository of results for integral analytical and detail design procedures. This paper outlines some of ARC's work in the creation, implementation and use of such data structures.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133216076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Topological Analysis for VLSI Circuits VLSI电路的拓扑分析
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600151
P. Losleben, K. Thompson
{"title":"Topological Analysis for VLSI Circuits","authors":"P. Losleben, K. Thompson","doi":"10.1109/DAC.1979.1600151","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600151","url":null,"abstract":"Algorithms are presented which use a bit map approach to derive connectivity checks, design rule checks, and electrical parameters for VLSI circuit artwork.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133870123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Automation of Manufacturing Planning, Shop Loading and Work Measurement in an Engineering Job Shop Environment 工程作业车间环境中制造计划、车间装载和工作测量的自动化
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600110
Edward J. Bresnen
{"title":"Automation of Manufacturing Planning, Shop Loading and Work Measurement in an Engineering Job Shop Environment","authors":"Edward J. Bresnen","doi":"10.1109/DAC.1979.1600110","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600110","url":null,"abstract":"A computer assisted system using standardized operations to prepare shop estimates, planning, status reporting, and work measurement information. Describes the development process, operational capabilities and current application at TRW Defense and Space Systems Group.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122554127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multiple Fault Diagnosis in Combinational Networks 组合网络中的多故障诊断
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600102
Charles W. Cha
{"title":"Multiple Fault Diagnosis in Combinational Networks","authors":"Charles W. Cha","doi":"10.1109/DAC.1979.1600102","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600102","url":null,"abstract":"The concept of prime faults is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a structurally equivalent fault with prime faults as its only components. Functional and structural masking and covering relations among faults are defined. These relations can be exploited to greatly simplify multiple fault analysis and their test generation. We present an efficient algorithm that generates a multiple fault detection test set and identifies redundancies. Suggestions for designing networks to yield a minimum number of tests in the multiple fault detection test set are also included.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129116248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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