{"title":"Symbolic Simulation for Correct Machine Design","authors":"W. Carter, W. Joyner, D. Brand","doi":"10.1109/DAC.1979.1600119","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600119","url":null,"abstract":"Program verification techniques which manipulate symbolic rather than actual values have been used successfully to find errors in implementations of computer designs. This paper describes symbolic simulation, a method similar to symbolic execution of programs, and its use in proving the correctness of machine architectures implemented in microcode. The procedure requires formal descriptions of machines at both the architectural and register transfer levels, but has been used to detect errors in implementation which often elude the standard test case approach.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116383597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A \"Lookahead\" Router for Multilayer Printed Wiring Boards","authors":"J. C. Foster","doi":"10.1109/DAC.1979.1600155","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600155","url":null,"abstract":"The layout of large multilayer printed wiring boards is a very complex and time-consuming process. The routing portion of the task in particular is difficult because of the number of connections to complete, the number of routing layers which can be used simultaneously and the large size and uniformity of the routing surfaces. The problem is generally well beyond the scope of a designer to grasp as a whole.\u0000 Automatic techniques for routing are important functions therefore in the multilayer layout process. A good deal of work has been done in the field. [1-5]\u0000 In this paper we will review a previous technique, describe some of its shortcomings, and present a new and more powerful method which has been successfully employed.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129636304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Application of Program Verification to Hardware Verification","authors":"J. Darringer","doi":"10.1145/62882.62926","DOIUrl":"https://doi.org/10.1145/62882.62926","url":null,"abstract":"The growing complexity of machine designs and costs of engineering changes are increasing the demand for tools and methods to detect errors earlier in the hardware development cycle. Because of similar concerns in the development of software there has been a great deal of work on methods for proving that a program satisfies a given specification. This paper examines one such program verification technique, based on the notion of symbolic execution , and then explores its application to the problem of establishing the correct behavior of a piece of hardware.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133398209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hughes S&CG Custom LSI Layouts - 'We Did it Our Way'","authors":"R. R. Rath","doi":"10.1109/DAC.1979.1600142","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600142","url":null,"abstract":"The following will describe a custom Large Scale Integration (LSI) microelectronic circuit layout software system written by the design engineers who use it. The key elements of the system are as follows: Layout is done with meaningful logical elements rather than at the geometrical mask level, thereby minimizing errors and requiring less skilled users to layout chips; computer generated check artwork and mask generation is produced direct]y from a logical layout rather than from digitized inputs; completion of the design loop is accomplished by automatic generation of an interconnection list from the actual graphical layout; programs are living, with new features and capabilities being added as requirements change; programs attempt first to solve the engineers problems and be user oriented, then to be elegant and efficient.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131671504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Koji Sato, Takao Nagai, Hiroyoshi Shimoyama, T. Yahara
{"title":"MIRAGE - A Simple-Model Routing Program for the Hierarchical Layout Design of IC Masks","authors":"Koji Sato, Takao Nagai, Hiroyoshi Shimoyama, T. Yahara","doi":"10.1109/DAC.1979.1600122","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600122","url":null,"abstract":"A simple-model routing program -MIRAGE- which is used in the hierarchical layout design of large scale IC masks is described together with some experimental results. By applying it hierarchically several times, satisfactory results can generally be obtained.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127424209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Unified Shapes Checker - A Checking Tool for LSI","authors":"C. McCaw","doi":"10.1109/DAC.1979.1600092","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600092","url":null,"abstract":"The designing and manufacturing techniques for integrated circuits have spawned a new free-form checking tool in IBM. This software tool has met the requirements of low cost for large volumes of data, breadth of function to support numerous methodologies, and depth of function for any specific technology.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115390039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Stonewalls: Experiments in Intelligent Drafting","authors":"Chris I. Yessios","doi":"10.5555/800292.811702","DOIUrl":"https://doi.org/10.5555/800292.811702","url":null,"abstract":"Algorithms for the derivation and drafting of stonewalls are discussed and illustrated. They are of two basic types. Stone-by-stone algorithms which simulate procedures known to be applied in practice, and joint-by-joint algorithms which pursue techniques aimed at deriving \"good\" results without simulating known procedures.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115929462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Incremental Processing Applied to Steinberg's Placement Procedure","authors":"H. Carter, M. Breuer, Z. A. Syed","doi":"10.5555/800292.811687","DOIUrl":"https://doi.org/10.5555/800292.811687","url":null,"abstract":"In this paper we indicate how the concept of incremental processing was applied to Steinberg's procedure for the placement of modules on a board. In this procedure Munkres' algorithm is repeatedly used to solve linear assignment problems. We consider each assignment problem (matrix) to represent an incremental change with respect to the previous one, and present new techniques for solving a new assignment problem given the results of the previous one. We refer to this new algorithm as the Incremental Steinberg Algorithm. Experimental results indicate that this new algorithm produces equally good results as the classical technique but at a substantial reduction in CPU time.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124373052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"LSI Layout Checking Using Bipolar Device Recognition Technique","authors":"C. S. Chang","doi":"10.1109/DAC.1979.1600094","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600094","url":null,"abstract":"Layout errors often result in nonfunctioning devices that still adhere to all layout tolerance rules. Reported here is a method for locating such errors in addition to the tolerance rule checking.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132056865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Generation of Hazard Free Tests Using the D-Algorithm in a Timing Accurate System for Logic and Deductive Fault Simulation","authors":"E. Kjelkerud, O. Thessén","doi":"10.1109/DAC.1979.1600106","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600106","url":null,"abstract":"It is described how a timing accurate system for logic and deductive fault simulation can be used in the forward tracing part of the D-algorithm. The logic simulation is used for the forward implication and the verification phases. The deductive fault simulator is used for D-propagation. Some results from executions of the test generation program are presented.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129078918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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