{"title":"The MIMOLA Design System: Detailed Description of the Software System","authors":"P. Marwedel","doi":"10.5555/800292.811692","DOIUrl":"https://doi.org/10.5555/800292.811692","url":null,"abstract":"A software system is described which aids in the design of digital processors with a topdown method. It takes the design language MIMOLA as its input. Input may be either a high level functional or a structural description of the hardware. The output is a description of the hardware on the block level. In the case of a high level functional input, the output contains a listing of the hardware which is necessary to execute the input together with utilization factors of the hardware units. The amount of creatable hardware may be limited in a declaration. If there is not enough hardware to execute the input statements in parallel, the necessary intermediate steps are inserted by the system and a corresponding functional description is presented.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128731295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The N. mPc System Description Facility","authors":"C. W. Rose, L. Rogers, R. Straubs","doi":"10.1109/DAC.1979.1600160","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600160","url":null,"abstract":"N. mPc [1], an interactive environment for the design and evaluation o f microprocessor-based systems, has been developed and implemented at Case Western Reserve University. N.mPc contains five separate tools which work together to produce a functional register transfer level simulation of multiple processor, heterogeneous target systems. A system block diagram is shown in Figure 1.\u0000 A meta assembler, metaMicro [2], allows the user to specify the Format, mnemonics, and associated bit patterns of the target instruction set. It maps mnemonics into bit strings, and outputs the instructions in a control/memory allocation graph which is machine independent.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123694375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Bristle Blocks: A Silicon Compiler","authors":"D. Johannsen","doi":"10.1145/62882.62903","DOIUrl":"https://doi.org/10.1145/62882.62903","url":null,"abstract":"Standard LSI Design Automation systems are database management systems that aid the circuit designer by organizing the collection of submodules that comprise a chip. This type of file system usually does not aid in the actual computation of silicon layout, and can hinder a designer with program constraints that have little or nothing to do with silicon constraints. The Bristle Block system is an attempt to create a silicon compiler that will perform the majority of the implementation computation while placing a minimum set of constraints on the designer. The goal of the Bristle Block system is to produce an entire LSI mask set from a single page, high level description of the integrated circuit.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124688047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Digital Logic at the Gate and Functional Level","authors":"P. Wilcox","doi":"10.1109/DAC.1979.1600114","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600114","url":null,"abstract":"Simulation, in several forms, is used extensively in present day circuit design. The various forms of simulation can be categorized in terms of level of detail offered, ranging from circuit level (transistors, capacitors, etc.) to timing level (e.g., MOTIS (1)) to logic gate level (NAND, NOR, etc.) to register transfer level. As with a microscope, increasing the resolution decreases the field of view. This 'law' imposes a constraint on the size of circuit a designer can simulate at any one level of detail, and most simulation programs are rigidly defined to operate at only one level. This leads to obvious problems, for example, when a circuit is mixed analog/digital, although some progress has been made on incorporating circuit level and gate level detail in one program(2). However, digital circuit sizes keep increasing and even now the gate level often offers too much resolution. To keep simulation costs down and to avoid overwhelming the macroscopic features of a circuit with irrelevant data another level of digital logic simulation is required. The various Hardware Description Languages(3) are too far removed from the gate level to be of much use here as they represent a very large, discrete jump from the gate level, when we would prefer a continuum of simulation resolution.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128187274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"DRAW3D: Time Sharing Graphic Interaction Using a Device-Space Buffer","authors":"Nicholas H. Weingarten, W. Kovacs, M. Corden","doi":"10.1109/DAC.1979.1600100","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600100","url":null,"abstract":"This paper presents the DRAW3D system, a three-dimensional interactive graphics program which operates in a time sharing environment. Key to this system is a device-space buffer which reduces demand for CPU power and enables a number of features not usually associated with non-refresh displays.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"2675 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129607445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SILOG: A Practical Tool for Large Digital Network Simulation","authors":"N. Giambiasi, A. Miara, D. Muriach","doi":"10.1109/DAC.1979.1600117","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600117","url":null,"abstract":"In this paper, the authors present a set of simulators for complex logical networks. On side of a briefly description of the simulators, emphasis is placed on developing user facilities.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121908557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cost Effective Data Entry Techniques for Design Automation","authors":"Jerry T. Harvel","doi":"10.1145/1061474.1061478","DOIUrl":"https://doi.org/10.1145/1061474.1061478","url":null,"abstract":"A major problem in automating the design of printed circuit boards and hybrids is an effective method of converting data from engineering documentation into machine readable form. The process is time consuming and error-prone, often representing 30% or more of the total design effort.This paper addresses several methods for capturing data from a schematic or logic diagram, and data entry. Traditional mediums, such as cards and tape, are reviewed. Conventional techniques, such as key-to-disc and key-to-tape are examined, and advanced techniques, such as graphic and voice data entry are also explored. Data conversion from other sources, such as existing wire lists, is also reviewed. The methods, techniques and procedures are investigated in detail.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128121865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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