{"title":"A Software System for Automated Placement and Wiring of LSI Chips","authors":"P. Wang, P. Bassett","doi":"10.1109/DAC.1979.1600127","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600127","url":null,"abstract":"This paper describes the Automated circuit Placement and Wiring programs used in IBM in conjunction with an FET Automatic Design System.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116672678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Evaluation of the N. mPc Design Environment","authors":"G. Ordy, F. Parke","doi":"10.1109/DAC.1979.1600162","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600162","url":null,"abstract":"Presents experimentally derived performance data on the N. mPc system. Data describing the type, size, and speed of simulations is presented. The implications of using the ISP' Hardware Description Language in constructing various models of the same components are considered. A set of design examples are presented to illustrate the range of simulation capabilities.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121728232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Introduction to Silicon Compilation","authors":"J. P. Gray","doi":"10.5555/800292.811726","DOIUrl":"https://doi.org/10.5555/800292.811726","url":null,"abstract":"Inexorable progress in device scaling has given rise to obvious increases in circuit complexity. There is the conjecture that the level of complexity in hardware designs is akin to the level of complexity associated with large software systems. If this is the case, then it follows that the design methods and expertise of systems analysts could be brought to bear on the complexity problems associated with large designs in silicon. Already there is evidence that structured hardware design, analogous to structured programming, is emerging in design philosophies that emphasize wiring management and hierarchical design development with regular structures [1]. However, if the expertise of the personnel in the software world is to be applied to silicon implementations of systems then there must be mechanisms that allow their participation in the design process. This could most effectively be achieved by allowing them to write programs which, when compiled, yield code that produces manufacturing data for silicon parts. Thus, taking a macroscopic view, there is a need to provide design tools that take a completely textual description of a design and translate it to layout data.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122768584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Minimum Width Routing of a 2-Row 2-Layer Polycell-Layout","authors":"Tatsuya Kawamoto, Y. Kajitani","doi":"10.1109/DAC.1979.1600121","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600121","url":null,"abstract":"This paper presents a new routing principle that leads to an algorithm to realize the minimum width of the 2-layer channel area between two rows of terminals to be interconnected. Besides the theoretical results, practically applicable routing algorithms based on our principle are developed.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121274674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Developments in Computer Simulation of Gate Level Physical Logic - a Tutorial","authors":"L. Bening","doi":"10.1109/DAC.1979.1600171","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600171","url":null,"abstract":"This paper discusses techniques developed for simulation of large physical logic systems at high speeds and with accurate timing.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121281909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. O'Neill, C. Savolaine, T. Thompson, J. M. Franke, R. Friedenson, E. Walsh, P. H. McDonald, J. R. Breiland, D. S. Evans
{"title":"Designers Workbench -- Efficient and Economical Design Aids","authors":"L. O'Neill, C. Savolaine, T. Thompson, J. M. Franke, R. Friedenson, E. Walsh, P. H. McDonald, J. R. Breiland, D. S. Evans","doi":"10.1109/DAC.1979.1600107","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600107","url":null,"abstract":"Designers Workbench is an interactive approach to design aids integration that overcomes most of the impediments that normally restrict the use of these aids. This paper first explores the problems encountered by users in trying to interface their design process with existing design aids and the problems of the design aids development organizations in meeting their users' needs. The design processes discussed include the electrical design, test development, and physical design for both computer architecture circuit pack design and custom electronics design, from the silicon level through the circuit pack level. Designers Workbench provides extensive on-line tutorials that greatly simplify the training of new users and buffers the user from the idiosyncracies of the computers on which the programs run. All job control, file management and data translations are provided automatically by the system. The design aids programs were left unchanged on their original computers and are accessed via a computer network. This reduced the initial development cost as well as providing a method for easy integration of any new programs that become available. Initial usage of DWB has indicated that this approach greatly increases the user acceptance of the design aids.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115537759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Global Router","authors":"J. Soukup","doi":"10.1145/62882.62905","DOIUrl":"https://doi.org/10.1145/62882.62905","url":null,"abstract":"The paper describes a new router which develops all connections simultaneously. Routes do not exist as lines, but rather as connected irregularly shaped areas which grow and retract in an amoeba-like manner. It is as if some routes are being rerouted, but it is all done at once. Because the cell map is scanned sequentially, the data handling and storage is vastly simplified.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124757584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electron Beam Lithography","authors":"F. S. Ozdemir","doi":"10.1109/DAC.1979.1600141","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600141","url":null,"abstract":"Electron beam lithography is a rapidly maturing technology that has opened the realm of submicron design to the semiconductor device and circuit designer. This improved pattern resolution has already yielded devices and circuits exhibiting higher density, higher operating frequency, and lower operating power than has been possible with other lithography methods. This paper discusses electron beam lithography and the devices and circuits that have been fabricated with this technology.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121385951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IC Specification Language","authors":"R. Ayres","doi":"10.1109/DAC.1979.1600124","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600124","url":null,"abstract":"This paper explores the use of computer languages for specifying ICs. Many different aspects of an IC may be specified via language such as logical function and layout. The logic function of an IC may be specified via boolean equations and the layout may be specified via shapes expressed with cartesian coordinates. With such specification, the computer can simulate the behavior of the IC and generate layouts with great precision.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128264702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Kawato, Takao Saito, Fumihiro Maruyama, T. Uehara
{"title":"Design and Verification of Large-Scale Computers by Using DDL","authors":"N. Kawato, Takao Saito, Fumihiro Maruyama, T. Uehara","doi":"10.1109/DAC.1979.1600137","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600137","url":null,"abstract":"This paper describes the total support system for DDL which has been approved by design engineers at Fujitsu. A simulator is used not only at register transfer level but also with gate level description. The translator generates gate level designs which are then optimized by designers. The verifier has powerful functions to detect conflicts in specification and its implementation.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"440 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120897420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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