{"title":"VLSI电路的拓扑分析","authors":"P. Losleben, K. Thompson","doi":"10.1109/DAC.1979.1600151","DOIUrl":null,"url":null,"abstract":"Algorithms are presented which use a bit map approach to derive connectivity checks, design rule checks, and electrical parameters for VLSI circuit artwork.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":"{\"title\":\"Topological Analysis for VLSI Circuits\",\"authors\":\"P. Losleben, K. Thompson\",\"doi\":\"10.1109/DAC.1979.1600151\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Algorithms are presented which use a bit map approach to derive connectivity checks, design rule checks, and electrical parameters for VLSI circuit artwork.\",\"PeriodicalId\":345241,\"journal\":{\"name\":\"16th Design Automation Conference\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1979-06-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"29\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"16th Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1979.1600151\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"16th Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1979.1600151","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Algorithms are presented which use a bit map approach to derive connectivity checks, design rule checks, and electrical parameters for VLSI circuit artwork.
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