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TMEAS, A Testability Measurement Program TMEAS，可测试性测量程序
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600103
J. Grason
{"title":"TMEAS, A Testability Measurement Program","authors":"J. Grason","doi":"10.1109/DAC.1979.1600103","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600103","url":null,"abstract":"TMEAS is a program that implements a testability measure for digital circuits. In this paper important features of TMEAS are described, including the circuit models it assumes, the testability measure it applies, and the various commands for analyzing the information generated by the testability measure. In addition, a discussion is provided of possible use modes for TMEAS and some examples of its use so far.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123869310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
A Placement Capability Based on Partitioning 一种基于分区的放置能力
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600145
L. I. Corrigan
{"title":"A Placement Capability Based on Partitioning","authors":"L. I. Corrigan","doi":"10.1109/DAC.1979.1600145","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600145","url":null,"abstract":"Placement is one of the numerous coordinated capabilities of the Hughes Computer-Aided Design (CAD) System. It is applicable to all of the technologies currently used to produce digital electronic assemblies and is particularly well suited to the allocation requirements of LSI and VLSI. The algorithm that is used iteratively selects sequences of module interchanges that minimize the number of signal crossings over a designated partition (line) across the assembly. An orderly succession of horizontal and vertical partitions causes a rearrangement of modules that facilitates routing, distributes wiring density and achieves minimal wirelength. The placement algorithm, its computational efficiency, its robust applicability, and the parts it plays within the Hughes CAD System are presented.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126602616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
An Interactive Layout System of Analog Printed Wiring Boards 模拟印刷线路板的交互式布局系统
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600158
K. Sahara, K. Kobori, I. Nishioka
{"title":"An Interactive Layout System of Analog Printed Wiring Boards","authors":"K. Sahara, K. Kobori, I. Nishioka","doi":"10.1109/DAC.1979.1600158","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600158","url":null,"abstract":"Apart from the layout of digital printed wiring boards (PWB's), no specific development has yet been reported on the layout of analog PWB's which contains not only placement and routing but also artwork to generate a variety of geometric wire patterns and assembly drawings, according to specifications. In this paper, we describe an interactive artwork system for such analog PWB's, which consists mainly of two programs; one is for generating wire patterns, and the other is for generating assembly drawings. This system has been in production use and has greatly contributed to the reduction of time and cost incurred in laying out wire patterns on analog PWB's.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128673075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Experimental Input System of Hand-Drawn Logic Circuit Diagram for LSI CAD 一种用于大规模集成电路CAD的手绘逻辑电路图实验输入系统
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600097
M. Ishii, Masanari Yamamoto, M. Iwasaki, H. Shiraishi
{"title":"An Experimental Input System of Hand-Drawn Logic Circuit Diagram for LSI CAD","authors":"M. Ishii, Masanari Yamamoto, M. Iwasaki, H. Shiraishi","doi":"10.1109/DAC.1979.1600097","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600097","url":null,"abstract":"This paper outlines a computer input system that reads hand-drawn LSI logic circuit diagrams. The system discriminates between connection lines and gate symbols and identifies the gate type. The input device can read diagrams drawn on sheets of paper up to size A2 (40 x 55 cm). Simple algorithms for discriminating between connection lines and gate symbols are also presented. These algorithms enable rapid processing of input data because there is no preliminary processing such as thinning or smoothing of lines. A performance test was made using a circuit diagram drawn on a size A4 (18 x 25 cm) sheet of paper. The results show that the input device can be put into practical use and, when combined with an interactive graphic system, can contribute to more efficient LSI circuit design.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117076214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Macrosimulation with Quasi-General Symbolic FET Macromodel and Functional Latency 准通用符号场效应管宏观模型与功能延迟的宏观仿真
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600112
H. Hsieh, N. Rabbat
{"title":"Macrosimulation with Quasi-General Symbolic FET Macromodel and Functional Latency","authors":"H. Hsieh, N. Rabbat","doi":"10.1109/DAC.1979.1600112","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600112","url":null,"abstract":"This paper evaluates our attempt to solve the large network analysis problems in the time domain by use of a simulation method with computation efficiency and program simplicity. We present a Quasi-general Symbolic FET Macromodel (QGSM) which can represent many different logic function gates; hence, the simulation program needs only one macromodel QGSM. We also discuss the Functional Latency Concept (FLC). With FLC we can avoid analyzing more inactive subnetworks to realize savings in CPU time. Finally, we describe a triple-iteration loop method which can be readily incorporated into the time-domain analysis. The experimental program exhibits topological flexibility, computational accuracy, and programming simplicity.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123500673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
New Algorithms for Grid-Less Routing of High Density Printed Circuit Boards 高密度印刷电路板无网格布线新算法
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600154
S. Pimont
{"title":"New Algorithms for Grid-Less Routing of High Density Printed Circuit Boards","authors":"S. Pimont","doi":"10.1109/DAC.1979.1600154","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600154","url":null,"abstract":"","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124896772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Computer Aided Ship Design and Numerically Controlled Production of Towing Tank Models 拖曳舱模型的计算机辅助船舶设计与数控制作
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600109
D. F. Rogers, F. Rodriguez, S. Satterfield
{"title":"Computer Aided Ship Design and Numerically Controlled Production of Towing Tank Models","authors":"D. F. Rogers, F. Rodriguez, S. Satterfield","doi":"10.1109/DAC.1979.1600109","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600109","url":null,"abstract":"A Computer Aided Ship Design (CASD) and a Computer Aided Manufacturing (CAM) program are described. The objective of the program is to provide the capability to design and manufacture towing tank models using interactive CASD and CAM techniques. A three dimensional interactive graphics device supported by a mini-computer is used to drive the design portion of the system. A microprocessor based graphics system, simply and directly interfaced to a CNC controller on the shop floor, is used to perform the postprocessing and drive the milling machine. Experiences with actual use of the system and the benefits derived from this use are discussed for an actual production job.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121575935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Hierarchical Modeling and Simulation in VISTA VISTA中的分层建模与仿真
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600144
Robert I. Gardner, P. Weil
{"title":"Hierarchical Modeling and Simulation in VISTA","authors":"Robert I. Gardner, P. Weil","doi":"10.1109/DAC.1979.1600144","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600144","url":null,"abstract":"The Missile Systems Group of Hughes Aircraft Company has defined the need for an LSI design capability that can produce very rapid designs of large digital and hybrid processors. These processor designs are characterized by:\u0000 100,000 gates/processor\u0000 10.000 gates/chip\u0000 10 LSI chips/processor\u0000 The goal for this LSI design capability is to be able to design and fabricate a system in 12 months elapsed time, with half of that time allocated to design and half allocated for mask making, chip processing, testing, and system integration (figure 1). A computer aided design system named VISTA (VLsI Simulation Test and Artwork) is currently being developed to answer this LSI design need (figure 2). One aspect of this design system is the modeling and simulation facility that supports hierarchical design.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117236559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Methods of Modelling Digital Devices for Logic Simulation 用于逻辑仿真的数字器件建模方法
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600113
E. Kjelkerud, O. Thessén
{"title":"Methods of Modelling Digital Devices for Logic Simulation","authors":"E. Kjelkerud, O. Thessén","doi":"10.1109/DAC.1979.1600113","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600113","url":null,"abstract":"Four methods of modelling digital devices in a logic simulator are described. Of special interest is a functional method based on the information given in data sheets which has made it possible to easily model many types of digital devices.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115416904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Two-Dimensional Placement Algorithm for the Master Slice LSI Layout Problem 主片LSI布局问题的二维布局算法
16th Design Automation Conference Pub Date : 1979-06-25 DOI: 10.1109/DAC.1979.1600081
S. Goto
{"title":"A Two-Dimensional Placement Algorithm for the Master Slice LSI Layout Problem","authors":"S. Goto","doi":"10.1109/DAC.1979.1600081","DOIUrl":"https://doi.org/10.1109/DAC.1979.1600081","url":null,"abstract":"This paper deals with the optimum placement of blocks on a two-dimensional cell-array, which minimizes the total routing length of signal sets. A new heuristic procedure, based on iterative improvement, is proposed. The procedure repeats random generation of an initial solution and its improvement by a sequence of local transformations. The best among the local optimum solutions is taken as a final solution. The iterative improvement method proposed here is different from the previous one in the sense that it considers interchanging more than two blocks at the same time and examines only a small portion of feasible solutions which has high probability of being better. Experimental results show this procedure gives better solutions than the best one up to now. The computation time for each local optimum solution grows almost linearly with regard to the number of blocks.","PeriodicalId":345241,"journal":{"name":"16th Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114909760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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