基于MOS/LSI掩模信息的电路仿真与时序验证

16th Design Automation Conference Pub Date : 1979-06-25 DOI:10.1109/DAC.1979.1600093

T. Akino, M. Shimode, Yukinaga Kurashige, Toshio Negishi

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引用次数: 7

摘要

开发了一个用于MOS/LSI掩模布局数据的掩模分析程序。该程序将一个芯片LSI中的所有掩码布局数据转换为相应的电路图。一种将大的随机逻辑电路划分成小的子电路的方法。结果表明，该方法充分利用了计算机时间和计算机存储的节省，可用于具有500个以上有源器件的随机逻辑电路的电路仿真和时序验证。

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Circuit Simulation and Timing Verification based on MOS/LSI Mask Information

A mask analysis program for MOS/LSI mask layout data has been developed. This program converts all the mask layout data in one chip LSI into the corresponding circuit schema. A partitioning method for the large random logic circuit divides it into small subcircuits. It is shown that this method takes full advantage of the savings both in computer time and computer storage for the circuit simulation and timing verification of the random logic circuit having more than 500 active devices.

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来源期刊

16th Design Automation Conference

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