Network on Chip Architectures最新文献_第5页

Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip 面向特定应用的片上分层网络的平面感知设计空间探索

Network on Chip Architectures Pub Date : 2011-12-04 DOI: 10.1145/2076501.2076508

D. Matos, G. Palermo, V. Zaccaria, C. Reinbrecht, A. Susin, C. Silvano, L. Carro

{"title":"Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip","authors":"D. Matos, G. Palermo, V. Zaccaria, C. Reinbrecht, A. Susin, C. Silvano, L. Carro","doi":"10.1145/2076501.2076508","DOIUrl":"https://doi.org/10.1145/2076501.2076508","url":null,"abstract":"Application-specific network-centric architectures (such as Networks on-Chip, NoCs) have recently become an effective solution to support high bandwidth communication in Multiprocessor Systems-on-Chip (MPSoCs). Moreover, the introduction of the hierarchy concept in the NoC design benefits from the main locality nature of the communication in MPSoC architectures. This paper presents a methodology to design Application Specific Hierarchical NoC (ASHiNoC) architectures considering foorplanning information. The presented approach targets heterogeneous clustered architectures where the intra-cluster communication is managed by a low-latency circuit-switched crossbar, while the inter-cluster communications are managed by a high-bandwidth packet-based NoC, allowing regulars topologies. The proposed design flow faces the problem by starting from the cluster selection down-to the foorplanning-aware estimation of the interconnect performances in terms of latency, power, area within each cluster and for the backbone NoC. Experimental results show that the AHiNoC architecture is able to guarantee an interconnection power and latency reduction of 49% and 33% respectively, at a cost of an area increment of 78% with respect to a flat topology version.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"42 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115873866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

ROBUST: a new self-healing fault-tolerant NoC router 鲁棒:一种新型自愈容错NoC路由器

Network on Chip Architectures Pub Date : 2011-12-04 DOI: 10.1145/2076501.2076504

J. Collet, A. Louri, V. Bhat, Pavan Poluri

{"title":"ROBUST: a new self-healing fault-tolerant NoC router","authors":"J. Collet, A. Louri, V. Bhat, Pavan Poluri","doi":"10.1145/2076501.2076504","DOIUrl":"https://doi.org/10.1145/2076501.2076504","url":null,"abstract":"This work addresses the general problem of making Network-on-Chips (NoCs) routers totally self-healing in massively defective technologies. There are three main contributions. First, we propose a new hardware approach based on Built-In Self-Test techniques and multi-functional blocks (called Universal Logic Blocks, ULBs) to autonomously diagnose permanent faults and repair faulty units. ULBs have the capability to assume the functionality of various functional units within the router through simple reconfiguration and thus enable the repair of multiple permanent faults within the NoC router. Second, we propose a new reliability metric and introduce a probabilistic model to estimate the router reliability improvement achieved by the protection circuitry. Third, we compare our architecture to two router architectures (Vicis and Bulletproof) and we show that our design provides superior reliability improvement especially in extremely defective nanoscale technologies (i.e., typically above 30% of faulty routers). The most striking result is that the self-healing of the routers enables maintaining the communications at fault levels, where it is normally impossible to preserve communications.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114254374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

A monitoring system for NoCs 国家石油公司监控系统

Network on Chip Architectures Pub Date : 2010-12-04 DOI: 10.1145/1921249.1921257

Leandro Fiorin, G. Palermo, C. Silvano

引用次数: 13

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology 纳米级硅技术约束下规则互连网络的拓扑对比

Network on Chip Architectures Pub Date : 2010-12-04 DOI: 10.1145/1921249.1921259

D. Ludovici, G. Gaydadjiev, Francisco Gilabert Villamón, M. E. Gómez, D. Bertozzi

{"title":"Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology","authors":"D. Ludovici, G. Gaydadjiev, Francisco Gilabert Villamón, M. E. Gómez, D. Bertozzi","doi":"10.1145/1921249.1921259","DOIUrl":"https://doi.org/10.1145/1921249.1921259","url":null,"abstract":"Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC). Such decision implies that a certain topology has to be selected to efficiently interconnect many cores on the chip. To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain. However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. This is due to the distinctive features of silicon technology design pitfalls. This work is a first milestone to bridge this gap, in fact, we propose a comprehensive analysis framework to assess k-ary n-mesh and C-mesh topologies at different level of abstractions, from system to layout level, while capturing implications of system and layout parameters across design hierarchy. When a certain topology proves to be slow due to long links crossing the chip, pipeline stages have been inserted to cope with such slow-down. Furthermore, costs of such speed-up technique have been evaluated to draw a comprehensive performance/area figure.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129157494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Enabling dynamic and programmable QoS in SoCs 在soc中启用动态和可编程的QoS

Network on Chip Architectures Pub Date : 2010-12-04 DOI: 10.1145/1921249.1921255

Daniele Mangano, G. Strano

引用次数: 5

Evolution of the server processor/platform architecture and the critical role of interconnect and future challenges 服务器处理器/平台架构的演变以及互连的关键作用和未来的挑战

Network on Chip Architectures Pub Date : 2010-12-04 DOI: 10.1145/1921249.1921251

G. Srinivasa

{"title":"Evolution of the server processor/platform architecture and the critical role of interconnect and future challenges","authors":"G. Srinivasa","doi":"10.1145/1921249.1921251","DOIUrl":"https://doi.org/10.1145/1921249.1921251","url":null,"abstract":"Peering at the next decade, will explore the processor and platform architecture challenges, as to what areas are undergoing enormous changes, while surveying the learning over the past two decades.\u0000 While exploring the next decade, will look at the processor internal interconnect evolution along with on chip resources starting with cache, memory controller and now being followed by IO integration vis-à-vis interchip multisocket interconnect at the platform level. Doing this, will outline the lessons learnt, what are the key challenges at macro and micro architecture level from the current perspective, where it is trending and some projections. I will describe the daily challenges and how we find sweet spots and surmount these in the interconnect area.\u0000 The talk will emphasize the three key vectors architects wrestle with Power, Performance and Cost at the processor and platform level and the critical role played by interconnect. The interconnect matters in architecting server that include power, flexibility, bandwidth and latency at macro and micro level. Interconnect could make or break in the product continuity and is a matter of serious consequence. We will explore how these affect the picture at a bigger level be it rack or cluster or data center.\u0000 With the current trend on Chip Multiprocessing mostly homogeneous that we have, will discuss the growth challenges that industry will face, what are the murky areas and state of SW and computing Industries key challenges. Will explore Heterogeneous computing, power and parallelization aspects and where we need a lot of research and focus.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121498411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip 基于强化学习的片上网络可重构容错偏转路由算法

Network on Chip Architectures Pub Date : 2010-12-04 DOI: 10.1145/1921249.1921254

Chaochao Feng, Zhonghai Lu, A. Jantsch, Jinwen Li, Minxuan Zhang

引用次数: 88

Netrace: dependency-driven trace-based network-on-chip simulation Netrace:依赖驱动的基于跟踪的片上网络仿真

Network on Chip Architectures Pub Date : 2010-12-04 DOI: 10.1145/1921249.1921258

Joel Hestness, Boris Grot, S. Keckler

引用次数: 145

A framework for designing congestion-aware deterministic routing 基于拥塞感知的确定性路由设计框架

Network on Chip Architectures Pub Date : 2010-12-04 DOI: 10.1145/1921249.1921261

A. E. Kiasari, A. Jantsch, Zhonghai Lu

引用次数: 9

A variable-pipeline on-chip router optimized to traffic pattern 可变管道片上路由器优化流量模式

Network on Chip Architectures Pub Date : 2010-12-04 DOI: 10.1145/1921249.1921263

Yuto Hirata, Hiroki Matsutani, M. Koibuchi, H. Amano

{"title":"A variable-pipeline on-chip router optimized to traffic pattern","authors":"Yuto Hirata, Hiroki Matsutani, M. Koibuchi, H. Amano","doi":"10.1145/1921249.1921263","DOIUrl":"https://doi.org/10.1145/1921249.1921263","url":null,"abstract":"Network-on-Chip (NoC) can be evaluated from various aspects, such as communication latency, throughput, and power consumption. The preference of these requirements depends on each application. An on-chip variable-pipeline (VP) router that can adapt to these requirements by dynamically reconfiguring its data path structure is proposed in this paper. In response to the communication pattern, it can change the pipeline structure, supply voltage, and operational frequency using the dynamic voltage and frequency scaling (DVFS). As the traffic load becomes high, the VP router uses a look-ahead two-cycle pipeline structure for exploiting the maximum frequency, while it behaves as a one-cycle router when a low latency is preferred. A three-cycle pipelined structure with an adaptive routing enables to dynamically avoid hotspots. Instead of a simple pipeline-stage unification which causes rapid decrease of the operating frequency, by speculatively executing multiple pipeline stages in parallel, the operating frequency gracefully decreases as the number of the pipeline stages increases. Simulation results show that the one-cycle mode offers the shortest communication latency, while the two-cycle mode achieves the highest throughput for SPLASH-2 benchmarks.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129084362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9