Network on Chip Architectures最新文献

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An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architecture 一种适用于常规NoC结构的高效能量和带宽感知映射算法

Network on Chip Architectures Pub Date : 2010-12-04 DOI: 10.1145/1921249.1921262

Saurabh Agrawal, Dhawal Sant, G. K. Sharma

引用次数: 6

Thread criticality support in on-chip networks 片上网络中的线程临界性支持

Network on Chip Architectures Pub Date : 2010-12-04 DOI: 10.1145/1921249.1921253

Yuho Jin, Ruisheng Wang, Woojin Choi, T. Pinkston

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引用次数: 5

Toward a science for future NoC design 走向未来NoC设计的科学

Network on Chip Architectures Pub Date : 2009-12-12 DOI: 10.1145/1645213.1645215

R. Marculescu

{"title":"Toward a science for future NoC design","authors":"R. Marculescu","doi":"10.1145/1645213.1645215","DOIUrl":"https://doi.org/10.1145/1645213.1645215","url":null,"abstract":"Traditionally, the design space exploration for systems-on-chip has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the design of the communication architecture plays a major role in defining the area, performance, and energy consumption of the overall system. From a technology point of view, this paradigm shift is meant to mitigate the problem of interconnects, keep the design complexity under control, and reduce costs. Since neither point-to-point, nor bus-based communication scale well in terms of power and performance figures, the network-on-chip architecture has been suggested as a promising solution for future multicore systems.\u0000 In this talk, we plan to address the concept of \"network\" in multiprocessor systems-on-chip and identify specific design principles and optimization techniques that are relevant to our research community. More precisely, we plan to discuss fundamental mathematical techniques that can be used to design, control, and optimize such networks in a rigorous manner at nanoscale. At the same time, we plan to also highlight alternatives to the conventional paradigm of network design. This new vision is based on rigorous developments in the field of statistical physics and information theory that allow us to model the network as a thermodynamical system. The hope is that this new modeling paradigm can enable not only capturing the intrinsic interactions among various network components, but also developing powerful techniques for predicting and optimizing the on-chip network behavior.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132723916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

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