走向未来NoC设计的科学

R. Marculescu
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引用次数: 1

摘要

传统上,片上系统的设计空间探索主要集中在手头问题的计算方面。然而,随着单个芯片上的组件数量及其性能的不断增加,通信架构的设计在定义整个系统的面积、性能和能耗方面起着重要作用。从技术的角度来看,这种模式的转变是为了缓解互连的问题,保持设计的复杂性在控制之下,并降低成本。由于点对点通信和基于总线的通信在功率和性能方面都不能很好地扩展,因此片上网络架构被认为是未来多核系统的一个有前途的解决方案。在这次演讲中,我们计划讨论多处理器片上系统中的“网络”概念,并确定与我们的研究社区相关的具体设计原则和优化技术。更确切地说,我们计划讨论可用于在纳米尺度上以严格的方式设计,控制和优化此类网络的基本数学技术。与此同时,我们还计划强调传统网络设计范式的替代方案。这一新愿景是基于统计物理学和信息论领域的严格发展,使我们能够将网络建模为热力学系统。希望这种新的建模范式不仅可以捕获各种网络组件之间的内在交互,而且还可以开发强大的技术来预测和优化片上网络行为。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Toward a science for future NoC design
Traditionally, the design space exploration for systems-on-chip has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the design of the communication architecture plays a major role in defining the area, performance, and energy consumption of the overall system. From a technology point of view, this paradigm shift is meant to mitigate the problem of interconnects, keep the design complexity under control, and reduce costs. Since neither point-to-point, nor bus-based communication scale well in terms of power and performance figures, the network-on-chip architecture has been suggested as a promising solution for future multicore systems. In this talk, we plan to address the concept of "network" in multiprocessor systems-on-chip and identify specific design principles and optimization techniques that are relevant to our research community. More precisely, we plan to discuss fundamental mathematical techniques that can be used to design, control, and optimize such networks in a rigorous manner at nanoscale. At the same time, we plan to also highlight alternatives to the conventional paradigm of network design. This new vision is based on rigorous developments in the field of statistical physics and information theory that allow us to model the network as a thermodynamical system. The hope is that this new modeling paradigm can enable not only capturing the intrinsic interactions among various network components, but also developing powerful techniques for predicting and optimizing the on-chip network behavior.
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