Network on Chip Architectures最新文献

Tree-Mesh Heterogeneous Topology for Low-Latency NoC 低延迟NoC的树-网格异构拓扑

Network on Chip Architectures Pub Date : 2014-12-13 DOI: 10.1145/2685342.2685346

Sung-Wook Han, Jinho Lee, Kiyoung Choi

引用次数: 10

On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration 在NoC设计探索中，RTL到TLM抽象有利于仿真性能和建模生产力

Network on Chip Architectures Pub Date : 2014-12-13 DOI: 10.1145/2685342.2685349

Sven Alexander Horsinka, Rolf Meyer, J. Wagner, R. Buchty, Mladen Berekovic

{"title":"On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration","authors":"Sven Alexander Horsinka, Rolf Meyer, J. Wagner, R. Buchty, Mladen Berekovic","doi":"10.1145/2685342.2685349","DOIUrl":"https://doi.org/10.1145/2685342.2685349","url":null,"abstract":"Growing demand to integrate more functionality into single-chip solutions require novel network-based interconnection models. The resulting increase in design complexity and strict time-to-market restrictions endanger the viability of Register Transfer Level (RTL) centric design processes in the future. To counteract these developments, the abstract design methodologies presented by Transaction Level Modeling (TLM 2.0/SystemC) are gaining popularity. With this paper, we demonstrate the benefits of raising the abstraction level by creating an adjustable Network on Chip (NoC) simulation model, satisfying the diverse needs of software and system engineers. Based on a proven and tested RTL NoC design, we applied modeling methods defined in the TLM 2.0 standard, creating flexible simulation model. It provides high timing accuracy, enabling precise behavioral and performance analysis. In addition, higher simulation speeds are achieved by adjusting the timing accuracy. The results demonstrate the advantages of variable simulation accuracy: simulation runs are accelerated by more than two orders of magnitude with performance and behavior assessment exposing a limited latency error of less than four clock cycles compared to the RTL model.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123602239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

The Connection-Then-Credit Flow Control Protocol for Networks-On-Chips: Implementation Trade-offs 片上网络的连接-信用流控制协议:实现权衡

Network on Chip Architectures Pub Date : 2014-12-13 DOI: 10.1145/2685342.2685348

M. Sallam, M. El-Kharashi, M. Dessouky

引用次数: 3

Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs 基于NoC的mpsoc中链路带宽感知回溯的动态任务映射

Network on Chip Architectures Pub Date : 2014-12-13 DOI: 10.1145/2685342.2685343

Changlin Chen, S. Cotofana

引用次数: 5

Guaranteed Services of the NoC of a Manycore Processor 多核处理器NoC的保证服务

Network on Chip Architectures Pub Date : 2014-12-13 DOI: 10.1145/2685342.2685344

B. Dinechin, Y. Durand, D. V. Amstel, Alexandre Ghiti

{"title":"Guaranteed Services of the NoC of a Manycore Processor","authors":"B. Dinechin, Y. Durand, D. V. Amstel, Alexandre Ghiti","doi":"10.1145/2685342.2685344","DOIUrl":"https://doi.org/10.1145/2685342.2685344","url":null,"abstract":"The Kalray MPPA®-256 processor (Multi-Purpose Processing Array) integrates 256 processing engine (PE) cores and 32 resource management (RM) cores on a single 28nm CMOS chip. These cores are distributed across 16 compute clusters and 4 I/O subsystems. On-chip communications and synchronization are supported by an explicitly routed dual data & control network-on-chip (NoC), with one node per compute cluster and 4 nodes per I/O subsystem, for a total of 32 nodes. The data NoC is dedicated to streaming data transfers and may operate with guaranteed services, thanks to non-blocking routers and flow regulation at the source node. Its architecture has been designed so that (σ, ρ) network calculus applies with minimal approximations.\u0000 Given a set of flows across this data NoC with predetermined routes, we formulate the problem of guaranteeing fair allocation of bandwidth across flows and we present bounds on the maximum transfer latency. By considering the architecture of the data NoC and by introducing conservative approximations, we show how this formulation can be transformed into a linear program. Solving this linear program is efficient and the quality of its solutions appears comparable to those of the original formulation, based on problem instances obtained from the cyclostatic dataflow compilation toolchain of the Kalray MPPA®-256 processor.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115405506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 62

OpenSoC Fabric: On-Chip Network Generator: Using Chisel to Generate a Parameterizable On-Chip Interconnect Fabric OpenSoC结构:片上网络生成器:使用凿子生成一个可参数化的片上互连结构

Network on Chip Architectures Pub Date : 2014-12-13 DOI: 10.1145/2685342.2685351

Farzad Fatollahi-Fard, D. Donofrio, George Michelogiannakis, J. Shalf

{"title":"OpenSoC Fabric: On-Chip Network Generator: Using Chisel to Generate a Parameterizable On-Chip Interconnect Fabric","authors":"Farzad Fatollahi-Fard, D. Donofrio, George Michelogiannakis, J. Shalf","doi":"10.1145/2685342.2685351","DOIUrl":"https://doi.org/10.1145/2685342.2685351","url":null,"abstract":"Recent advancements in technology scaling have sparked a trend towards greater integration with large-scale chips containing thousands of processors connected to memories and other I/O devices using non-trivial network topologies. Software simulation suffers from long execution times or reduced accuracy in such complex systems, whereas hardware RTL development is too time-consuming. We present OpenSoC Fabric, a parameterizable and powerful on-chip network generator for evaluating future large-scape chip multiprocessors and SoCs. OpenSoC Fabric leverages a new hardware DSL, Chisel, which contains powerful abstractions provided by its base language, Scala, and generates both software (C++) and hardware (Verilog) models from a single code base. This is in contrast to other tools readily available which typically provide either software or hardware models, but not both. The OpenSoC Fabric infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, is open-source, and uses object-oriented design and functional programming to make functionality extension as easy as possible.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126964749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

An Energy Efficient Load Balancing Selection Strategy for Adaptive NoC Routers 自适应NoC路由器的高效负载均衡选择策略

Network on Chip Architectures Pub Date : 2014-12-13 DOI: 10.1145/2685342.2685350

John Jose, Bivil M. Jacob, Hashim P. Kamal

引用次数: 2

Evaluating the Feasibility of Wireless Networks-on-Chip Enabled by Graphene 评估石墨烯实现无线片上网络的可行性

Network on Chip Architectures Pub Date : 2014-12-13 DOI: 10.1145/2685342.2685345

S. Abadal, Albert Mestres, M. Iannazzo, J. Solé-Pareta, E. Alarcón, A. Cabellos-Aparicio

引用次数: 8

A Novel Partitioning Algorithm for Optimizing Neuron-to-Neuron Pathways through NoC in BMI 一种通过NoC优化BMI神经元间通路的新划分算法

Network on Chip Architectures Pub Date : 2014-12-13 DOI: 10.1145/2685342.2685347

Jim Ng, T. Mak

{"title":"A Novel Partitioning Algorithm for Optimizing Neuron-to-Neuron Pathways through NoC in BMI","authors":"Jim Ng, T. Mak","doi":"10.1145/2685342.2685347","DOIUrl":"https://doi.org/10.1145/2685342.2685347","url":null,"abstract":"To study the complex interactions between neurons in a large-scale neural network and perform neural rehabilitation to restore the function of a damaged neural organ, an efficient interface and an underlying processing unit is to be developed to cope with the high demand of massive realtime signal processing. The combination of Micro-Electrode Array(MEA) and Network-on-Chip(NoC) makes it possible to build a powerful monitoring, signal relaying and stimulation simulation system. This Brain Machine Interface (BMI) system is able to capture, relay and response to neural signal in a biologically realistic way. To achieve this goal, the traffic in the NoC is managed in an efficient way to minimize the packet delay. Moreover, to raise the scalability of the system given the time delay constraint, a novel partitioning algorithm is presented to minimize the traffic generated. Existing partitioning algorithms can be used to archive this aim, but they are inefficient when applied to this novel scenario. The proposed partitioning algorithm is designed specifically for this scenario and thus is able to reduce the traffic generated in the NoC by 25% on average. The power consumption is also reduced significantly.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126686402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

User satisfaction aware routing decisions in NOC NOC中基于用户满意度的路由决策

Network on Chip Architectures Pub Date : 2013-12-08 DOI: 10.1145/2536522.2536531

Swamy D. Ponpandi, A. Tyagi

引用次数: 1