Network on Chip Architectures最新文献_第2页

Empirical and theoretical lower bounds on energy consumption for networks on chip 片上网络能量消耗的经验和理论下限

Network on Chip Architectures Pub Date : 2013-12-08 DOI: 10.1145/2536522.2536535

George B. P. Bezerra, D. Arnold, S. Forrest

引用次数: 0

Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth 三维NoC垂直带宽有限的最优自适应路由研究

Network on Chip Architectures Pub Date : 2013-12-08 DOI: 10.1145/2536522.2536534

Gunhee Lee, Jinho Lee, Kiyoung Choi

引用次数: 0

Millimeter (mm)-wave wireless NoC as interconnection backbone for multicore chips: promises and challenges 毫米波无线NoC作为多核芯片的互连骨干:承诺与挑战

Network on Chip Architectures Pub Date : 2013-12-08 DOI: 10.1145/2536522.2536524

P. Pande

{"title":"Millimeter (mm)-wave wireless NoC as interconnection backbone for multicore chips: promises and challenges","authors":"P. Pande","doi":"10.1145/2536522.2536524","DOIUrl":"https://doi.org/10.1145/2536522.2536524","url":null,"abstract":"The continuing progress and integration levels in silicon technologies make complete end-user systems on a single chip possible. This massive level of integration makes modern multi-core chips all pervasive in domains ranging from weather forecasting, astronomical data analysis, and biological applications to consumer electronics and smart phones. NoCs have emerged as communication backbones to enable a high degree of integration in multi-core SoCs. Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multi-hop communications, wherein the data transfer between far-apart blocks causes high latency and power consumption. The latency, power consumption, and interconnect routing problems of NoCs can be simultaneously addressed by replacing multi-hop wired paths with high-bandwidth single-hop long-range wireless links. Recent investigations have established that the silicon integrated on-chip antenna operating in the millimeter wave range of a few tens to one hundred GHz is now a viable technology. Coupled with significant advances in mm-wave transceiver design, this opens up new opportunities for detailed investigations into wireless NoCs (WiNoCs). This talk will present methodologies and challenges for designing WiNoC architectures.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127653793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploiting emerging technologies for nanoscale photonic networks-on-chip 利用纳米级片上光子网络的新兴技术

Network on Chip Architectures Pub Date : 2013-12-08 DOI: 10.1145/2536522.2536525

Jun Pang, C. Dwyer, A. Lebeck

引用次数: 5

Design space exploration for streaming applications on multiprocessors with guaranteed service NoC 多处理器流应用的设计空间探索，保证服务NoC

Network on Chip Architectures Pub Date : 2013-12-08 DOI: 10.1145/2536522.2536527

U. Mirza, F. Gruian, K. Kuchcinski

引用次数: 6

LEF: long edge first routing for two-dimensional mesh network on chip LEF:片上二维网状网络的长边第一路由

Network on Chip Architectures Pub Date : 2013-12-08 DOI: 10.1145/2536522.2536530

Ryosuke Sasakawa, Kenji Kise

引用次数: 5

Costs and benefits of flexibility in spatial division circuit switched networks-on-chip 片上空间划分电路交换网络灵活性的成本与效益

Network on Chip Architectures Pub Date : 2013-12-08 DOI: 10.1145/2536522.2536526

Ahsen Ejaz, A. Jantsch

{"title":"Costs and benefits of flexibility in spatial division circuit switched networks-on-chip","authors":"Ahsen Ejaz, A. Jantsch","doi":"10.1145/2536522.2536526","DOIUrl":"https://doi.org/10.1145/2536522.2536526","url":null,"abstract":"Although most Network-on-Chip (NoC) designs are based on Packet Switching (PS), the importance of Circuit Switching (CS) should not be underestimated. Many MPSoC executing real-time applications require an underlying communication backbone that can relay messages from one node to another with guaranteed throughput. Compared to PS, CS can provide guaranteed throughput with lower area and power overheads. It is also highly suited for applications where nodes transfer long messages. Spatial Division Multiplexing (SDM) can allow more efficient use of available network resources by dividing them among multiple simultaneous transactions. The network developed by Vali [1] has three design variations based on the number of sub-channels, has a predictable connection setup time, and uses CS to provide guaranteed throughput once a connection is established. In this paper we use this network as a basis to study the effect of flexibility based on SDM, on the performance of a CS networks. A network evaluation platform has been developed to configure and evaluate networks with a maximum of 8 sub-networks, with each subnetwork comprising of 1, 2 or 4 sub-channels. We show that under uniform traffic pattern with requests of uniform random bandwidth (BW) requirement, a less flexible network outperforms a network with higher flexibility due to a phenomenon we call 'stray requests'. We conclude this paper by showing that under high network traffic, performance of our flexible networks can be as much as 113% better than HAGAR [2] and Liu's [3] network.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129401129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A first effort for a distributed segment-based approach on self-assembled nano networks 基于自组装纳米网络的分布式分段方法的首次尝试

Network on Chip Architectures Pub Date : 2013-12-08 DOI: 10.1145/2536522.2536532

V. Catania, Andrea Mineo, Salvatore Monteleone, Davide Patti

{"title":"A first effort for a distributed segment-based approach on self-assembled nano networks","authors":"V. Catania, Andrea Mineo, Salvatore Monteleone, Davide Patti","doi":"10.1145/2536522.2536532","DOIUrl":"https://doi.org/10.1145/2536522.2536532","url":null,"abstract":"In this paper we present DiSR, a first effort for a distributed segment-based approach to routing and defect mapping in a nano-scale, topology agnostic scenario based on DNA self-assembly. The main aim is exploiting the already-proven qualities of segment-based routing without neither requiring a topology graph as input, nor needing a centralized algorithm to configure network paths. After introducing the conceptual elements and the execution model of DiSR, we show how the opensource Nanoxim platform has been used to evaluate the proposed approach in the process of discovering irregular network topology while establishing network segments. Results show how DiSR still preserves some important properties (coverage, defect tolerance, scalability) while avoiding centralized tree-based broadcasting and resource hungry solutions such as virtual channels and hardware redundancy. Finally, we analyzed a first, not yet optimised gate-level hardware implementation of the required control logic and storage for DiSR, demonstrating a relatively acceptable impact ranging from 10 to about 20% of the budget of transistors available for each node.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"28 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120879935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

On multicast for dynamic and irregular on-chip networks using dynamic programming method 用动态规划方法研究动态和不规则片上网络的组播

Network on Chip Architectures Pub Date : 2013-12-08 DOI: 10.1145/2536522.2536529

W. Zong, Xiaohang Wang, T. Mak

{"title":"On multicast for dynamic and irregular on-chip networks using dynamic programming method","authors":"W. Zong, Xiaohang Wang, T. Mak","doi":"10.1145/2536522.2536529","DOIUrl":"https://doi.org/10.1145/2536522.2536529","url":null,"abstract":"Mutlicast is an intrinsic communication pattern in emerging applications including the Internet service, bio-inspired computing, online data analysis, etc. Providing hardware multicast largely boosts system performance and reduce power consumption for these applications running on many-core systems. However, many-core systems suffer from dynamically changing topologies, which can be caused by traffic isolation, power management and faults. Links and routers may be removed from a subnetwork or added to a subnetwork, this imposes the routers to alter the routing paths accordingly to make the routing energy efficient. Furthermore an energy efficient multicast scheme that fits to any topology is required in this scenario. Most existing fault tolerant routings cannot detect and found energy efficient communication paths effectively for both unicast and multicast. In this work, a lightweight network couples with on-chip routers is used to propagates topological information. The shortest path between any node pair is also computed in this network using dynamic programming method. Unicast packets are routed along a shortest path to its destination, and multicast packet copies at each router is minimized based a rule called minimal replication to reduce multicast link occupation and energy consumption. Simulation results show that the proposed NoC routes 96% packets to their destinations if there exists a path, and demonstrate 40% lower latency and 30% power consumption compared with Stochastic communication. The extra hardware cost to build optimal multicast path is estimated to occupy less than 5% of the total area of a router.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128440593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

On heterogeneous network-on-chip design based on constraint programming 基于约束规划的异构片上网络设计

Network on Chip Architectures Pub Date : 2013-12-08 DOI: 10.1145/2536522.2536528

A. Demiriz, N. Bagherzadeh

引用次数: 2