Network on Chip Architectures最新文献

{"title":"Modeling and analyzing timing faults in transaction level SystemC programs","authors":"Reza Hajisheykhi, Ali Ebnenasir, S. Kulkarni","doi":"10.1145/2536522.2536533","DOIUrl":"https://doi.org/10.1145/2536522.2536533","url":null,"abstract":"Since SoC (System on Chip) and NoC (Network on Chip) systems are getting more complex everyday, they are subject to different types of faults including timing faults. Timing has a significant importance in NoC systems. However, their fault-affected models are not studied extensively. In this paper, we present a method for modeling and analyzing timing faults in SystemC Transaction Level Modeling (TLM) programs. The proposed method includes three steps, namely timed model extraction, fault modeling and timed model checking. We use UPPAAL timed automata to formally model the SystemC TLM programs and monitor how the models behave in the presence of timing faults. We analyze our method using a case study. This case study utilizes loosely-timed coding style, which has a loose dependency between timing and data.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124014137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips","authors":"Hanmin Park, Kiyoung Choi","doi":"10.1145/2401716.2401728","DOIUrl":"https://doi.org/10.1145/2401716.2401728","url":null,"abstract":"This paper presents the position-based weighted round-robin arbitration for equality of service in many-core network-on-chips employing a deterministic routing algorithm. We concentrate on the network saturation induced by the hot-spot traffic that occurs when the threads running on the system simultaneously access shared data, global shared locks, etc. It exploits the deterministic properties of the interconnect network---the topology and the routing algorithm. This leads to the omission of additional information in packet headers, compared to the previous approaches. The hardware overhead is minimal, requiring only the weight counters in addition to a typical round-robin arbiter. Compared with the previous work, the proposed algorithm also reduces the critical path delay due to its simplicity. Although designed against the hot-spot traffic, the proposed arbitration scheme shows little performance degradation under other traffic patterns in terms of the average latency and the saturation throughput.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124670441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors","authors":"L. Ramini, D. Bertozzi","doi":"10.1145/2401716.2401723","DOIUrl":"https://doi.org/10.1145/2401716.2401723","url":null,"abstract":"There is still a significant gap between the optical network-on-chip (NoC) concept and a mature interconnect technology with practical relevance. Current research aims at bridging this gap by evolving basic optical components and by developing ad-hoc design tools to enable their use for system-level design. This paper points out another cause for the design predictability gap of optical NoC topologies, namely the physical placement of network interfaces in the target floorplan. Building on this awareness, the paper compares power efficiency of the most relevant topologies proposed so far for wavelength-routed optical NoCs in the context of a 3D-stacked multi-core processor.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"27 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126278405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A high-efficiency low-cost heterogeneous 3D network-on-chip design","authors":"T. Xu, P. Liljeberg, J. Plosila, H. Tenhunen","doi":"10.1145/2401716.2401725","DOIUrl":"https://doi.org/10.1145/2401716.2401725","url":null,"abstract":"In this paper, we propose and analyze a heterogeneous Three Dimensional (3D) Network-on-Chip (NoC) design based on the optimized placement of vertical connections. NoC paradigm is expected to be the solution of future multicore processors, while 3D NoC extends the on-chip network vertically. Most previous research focus on symmetric, homogeneous, fully-connected 3D NoC designs. However, these designs may not be suitable for production and the market. The adoption of a 3D NoC design depends on the performance, power consumption and manufacturing cost of the chip. Here, we propose a 3D NoC design which improves performance, reduces power consumption and manufacturing cost. First, the vertical connections between layers are reduced and placed optimally. Second, the routers and links are redesigned to fit the heterogeneity nature of the network. The 3D NoC design is discussed with two configurations. We model a 64-core 3D NoC based on state-of-the-art 2D NoCs. A cycle accurate full system simulator is used for benchmark results. Experiments show that under different applications, the average execution times in two configurations are reduced by 5.5% and 20.7% respectively, compared with the homogeneous design. The average energy delay product of our design can achieve twice as better comparing with the diagonal heterogeneous design. This paper provides an inspiration for designing high performance, low power consumption and manufacturing cost 3D NoCs.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116234354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip","authors":"Nizar Dahir, Ra'ed Al-Dujaily, A. Yakovlev, Petros Missailidis, T. Mak","doi":"10.1145/2401716.2401724","DOIUrl":"https://doi.org/10.1145/2401716.2401724","url":null,"abstract":"This paper proposes a new method for designing adaptive routing algorithms for 3D networks-on-chip (NoCs). This method is based on extending the existing 2D turn model adaptive routing to a 3D scenario. A 3-D plane-balanced approach with maximal degree of adaptiveness is achieved by applying a well-defined set of rules for different strata of the 3D NoC. The proposed method is applicable to any of the turn models. In this paper, we employ odd-even turn model as a basis for introducing the proposed strategy. Experimental results show that the new 3D odd-even can achieve up to 23.8% improvement in throughput over conventional odd-even approach. The improvement is consistent for different traffic types. The proposed method enables a new avenue to explore adaptive approaches for future large-scale 3D integration.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117307472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Network on metachip architectures","authors":"Ismo Hänninen, Wayne Buckhanan, M. Niemier, G. Bernstein","doi":"10.1145/2401716.2401719","DOIUrl":"https://doi.org/10.1145/2401716.2401719","url":null,"abstract":"The size of systems on a chip is limited by our ability to design and fabricate such systems, staying within the appropriate costs depending on the application. In this paper, we propose a divide-and-conquer approach, Quilt Packaging®, to be utilized for reducing the fabrication costs of large digital systems by partitioning them into a quilted \"metachip\" that offers integration density and performance merits surpassing the traditional system-on-chip. The physical partitioning and the network-on-a-quilt are closely linked, and should be designed concurrently. For this purpose, we present calculations on the silicon cost of the interconnects and partitioning, discuss the network granularity, and propose a multiprocessor design around a quilted modular network, offering novel techniques to improve the performance and enable true heterogeneous integration. Specifically, the silicon costs of the quilting method are demonstrated to be around 1% of the chip area, while the yield benefits can be in the tens of percents regime. The metachip concept enables the combination of standard high-density memory technologies and wide-bus access with improved performance, typically at least doubling the amount of memory vs. single-chip CMOS. Our modular quilted network enables the integration of non-CMOS chips into the quilt.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126134877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Junction based routing: a scalable technique to support source routing in large NoC platforms","authors":"Shabnam Badri, Rickard Holsmark, Shashi Kumar","doi":"10.1145/2401716.2401727","DOIUrl":"https://doi.org/10.1145/2401716.2401727","url":null,"abstract":"To support communication among hundreds of cores on a chip, on-chip communication must be well organized. In the embedded systems using such a chip, the communication patterns can be profiled off-line and routing can be well planned. Source routing has been shown to be suitable in such contexts [1]. However, source routing has one serious drawback of overhead for storing the path information in header of every packet. This disadvantage becomes worse as the size of the network grows. In this paper we propose a technique, called Junction Based Routing (JBR), to remove this limitation. In the proposed technique, path information for only a few hops is stored in the packet header. With this information, either the packet reaches the destination, or reaches a junction from where the path information for on-ward path is picked up. There are many interesting issues related to this approach. We discuss and solve two important issues related to JBR, namely, the required number of junctions and their positions and path computation for efficient deadlock-free routing. A simulator has been developed to evaluate the performance of JBR and compare it with simple source routing. We observe that JBR has slightly worse performance as compared to pure source routing for packets with large payload. But JBR has a potential of higher performance for packets with small payloads.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"87 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128963635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A structural analysis of evolved complex networks-on-chip","authors":"H. Chung, Anusha Pai Asnodkar, C. Teuscher","doi":"10.1145/2401716.2401721","DOIUrl":"https://doi.org/10.1145/2401716.2401721","url":null,"abstract":"Designing large-scale heterogeneous Networks-on-Chip (NoCs) for irregular applications often involves sophisticated optimization techniques that lead to unstructured networks. Such networks are hard to understand because they were not built with common engineering knowledge. In this paper we use tools from complex network analysis, such as community detection, and small-worldness, to analyze the structure of optimized heterogeneous NoCs. Our results show that communities evolve robustly and that heterogeneous link types are efficiently establishing inter- and intra-subnet connections. We confirm that networks optimized under cost pressure are more modular. Finally, we determine the small-worldness and observe that small-world networks evolve as a result of a trade-off between performance and cost. Our results are relevant for the understanding of heterogeneous NoCs and for designing optimal communication fabrics for emerging technologies.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124394831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low power flitwise routing in an unidirectional torus with minimal buffering","authors":"Jörg Mische, T. Ungerer","doi":"10.1145/2401716.2401730","DOIUrl":"https://doi.org/10.1145/2401716.2401730","url":null,"abstract":"State-of-the-art Network on Chips (NoCs) provide a high throughput and low latency by sending packets of data through a mesh topology, using virtual channels and wormhole flow control. The downside of this technology is a high area and energy consumption due to many buffers, large crossbars and a complex arbitration logic within the routers.\u0000 In our approach, we avoid flow control and complex analysis of the head flit by sending single standalone flits instead of large packets of flits. As the order of flits is preserved between sending and receiving node, large data blocks can be sent anyway. The complexity of the router is further reduced by using an unidirectional 2D torus instead of a mesh, which reduces the number of router ports from 5 to 3. The flits are X-Y-routed and transported bufferless, as long as they stay within one dimension. Consequently there is only one FIFO per router, which buffers flits when they turn from X to Y direction. In terms of throughput and latency the so-called paternoster router is comparable with a conventional router with two virtual channels, but it consumes 50% less energy and 60% less area.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125337850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Developing survival instincts in computing systems","authors":"A. Yakovlev","doi":"10.1145/2401716.2401717","DOIUrl":"https://doi.org/10.1145/2401716.2401717","url":null,"abstract":"Complex information and communication systems have been studied for a long time. Many approaches and methodologies exist to date. Amongst the properties of interest in those studies the prominent place is occupied by the property of systems to stay alive and functional in spite of harsh environmental conditions that may surround them. Typically such conditions are assumed to generate higher rates of errors such as those that are caused by radiation. They are considered mostly in the scope of information processing, and to a lesser extent in the domain of resource availability, for example, the availability of energy. While the system may remain fully functional under the nominal conditions of energy supply, its behaviour may be highly unpredictable when the energy flow to the system is impaired for one or another reason. Design of systems with varying power modes is a rapidly emerging area of research, and it comes from many different directions; for example, intelligent autonomous systems, systems with energy harvesting, green computing etc. Much of this research is about systems that are still sufficiently complex that even their most energy-frugal mode of action still requires a certain stable level of energy flow. What about systems that have to 'live on the poverty line', the conditions in which power levels drop to zero and systems that have to self-recover upon the arrival of the 'first glimpse of sunlight'?\u0000 In this presentation we shall be looking at the first glimpses of, perhaps, still naive, approaches to building computing systems whose power sources can be defined in a wide band of modes. Such systems will effectively need survival instincts as part of their intrinsic characteristic. An important element of this new design discipline is a close proximity of the design methods required for power conditioning and those necessary for computational blocks as the latter form the load for the power chain. This proximity and associated holisticity drives for codesign, which involves new methods for modelling, simulation, synthesis and hardware and software implementation. This talk will address a number of paradigms for such designs, such as energy-modulated computing, power-proportional, power-adaptive and elastic system design, and present examples of problems formulated and solutions obtained in the context of research on the new generation of systems with energy-harvesting. Amongst those examples are a power-proportional FFT unit, a static RAM that can operate under varying power levels, reference free voltage sensor, power electronics with capacitor banks. One of the most critical aspects of any system design is its communication fabric. Its survival in power-deficient modes, in whatever form or shape, is essential for keeping even the most basic functions alive in the system. The talk will invite the audience to speculate on what sort of heuristics and principles of design of the interconnect fabric can be developed to support its ac","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125910251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}