A high-efficiency low-cost heterogeneous 3D network-on-chip design

Abstract

In this paper, we propose and analyze a heterogeneous Three Dimensional (3D) Network-on-Chip (NoC) design based on the optimized placement of vertical connections. NoC paradigm is expected to be the solution of future multicore processors, while 3D NoC extends the on-chip network vertically. Most previous research focus on symmetric, homogeneous, fully-connected 3D NoC designs. However, these designs may not be suitable for production and the market. The adoption of a 3D NoC design depends on the performance, power consumption and manufacturing cost of the chip. Here, we propose a 3D NoC design which improves performance, reduces power consumption and manufacturing cost. First, the vertical connections between layers are reduced and placed optimally. Second, the routers and links are redesigned to fit the heterogeneity nature of the network. The 3D NoC design is discussed with two configurations. We model a 64-core 3D NoC based on state-of-the-art 2D NoCs. A cycle accurate full system simulator is used for benchmark results. Experiments show that under different applications, the average execution times in two configurations are reduced by 5.5% and 20.7% respectively, compared with the homogeneous design. The average energy delay product of our design can achieve twice as better comparing with the diagonal heterogeneous design. This paper provides an inspiration for designing high performance, low power consumption and manufacturing cost 3D NoCs.