Network on Chip Architectures最新文献_第4页

Variability-tolerant NoC link design 可变容错NoC链路设计

Network on Chip Architectures Pub Date : 2012-12-01 DOI: 10.1145/2401716.2401729

E. Gawish, M. El-Kharashi, Mohamed Fathy Abu Elyazeed

引用次数: 4

Surface wave communication system for on-chip and off-chip interconnects 用于片内和片外互连的表面波通信系统

Network on Chip Architectures Pub Date : 2012-12-01 DOI: 10.1145/2401716.2401720

Ammar Karkar, Ra'ed Al-Dujaily, A. Yakovlev, K. Tong, T. Mak

引用次数: 14

B2RAC: a physical express link addition methodology for network on chip 片上网络的物理快速链路添加方法

Network on Chip Architectures Pub Date : 2011-12-04 DOI: 10.1145/2076501.2076505

Jiajia Jiao, Yuzhuo Fu

引用次数: 4

Floodgate: application-driven flow control in network-on-chip for many-core architectures 闸门:应用程序驱动的流量控制在多核架构的片上网络

Network on Chip Architectures Pub Date : 2011-12-04 DOI: 10.1145/2076501.2076503

Yoshi Shih-Chieh Huang, Huang-Yu Liu, Yuan-Ying Chang, C. King, S. Tseng

{"title":"Floodgate: application-driven flow control in network-on-chip for many-core architectures","authors":"Yoshi Shih-Chieh Huang, Huang-Yu Liu, Yuan-Ying Chang, C. King, S. Tseng","doi":"10.1145/2076501.2076503","DOIUrl":"https://doi.org/10.1145/2076501.2076503","url":null,"abstract":"With the prevalence of multi- and many-core architecture, network-on-chip (NoC) is becoming the main paradigm for on-chip interconnection. However, the performance of NoCs can be degraded significantly if the network flow is not controlled properly. Most previous solutions have tried to detect network congestion by monitoring the hardware status of the network switches or links. Unfortunately, such strategies rely on the backpressure of the traffic flows for congestion detection and may be too slow to respond. This paper proposes a proactive strategy which predicts the global, end-to-end traffic patterns of the running application and takes preventive flow control actions to avoid congestions. The proposed system entails an application-level prediction table for accurate traffic prediction and a packet injection scheduler for congestion avoidance. The proposed scheme is evaluated by a trace-driven simulator with synthetic traffic traces as well as a real application trace of an instance in the SPLASH-2 benchmark. The results show the superior performance of the proposed scheme with negligible execution overhead.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124710569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Selecting the optimal system: automated design of application-specific systems-on-chip 选择最佳系统:针对特定应用的片上系统的自动化设计

Network on Chip Architectures Pub Date : 2011-12-04 DOI: 10.1145/2076501.2076510

Oscar Almer, Miles Gould, Björn Franke, N. Topham

{"title":"Selecting the optimal system: automated design of application-specific systems-on-chip","authors":"Oscar Almer, Miles Gould, Björn Franke, N. Topham","doi":"10.1145/2076501.2076510","DOIUrl":"https://doi.org/10.1145/2076501.2076510","url":null,"abstract":"Specialising Systems-on-Chip (SOCs) for a particular application is an effective way of increasing the performance achievable for a given level of energy consumption. In fact, silicon manufacture costs are low enough that small, custom, entirely digital designs, up to and including multi-core microprocessor designs, can be manufactured cheaply in short manufacturing runs. Non-recurring engineering (Nre) costs are still prohibitive due to the high level of experience required from the design engineer and the vast size of the design space. This is even true when only pre-verified Commercial Off-the-Shelf (Cots) Intellectual Property (ip) blocks are used in the SoC design. In this paper we present a novel machine-learning based method of generating an application-specific SoC design and configuration. This approach is fully automated and can generate near-optimal application-specific SoC designs within hours rather than weeks and, hence, reduce both Nre costs and time-to-market significantly. Our methodology profiles key application characteristics using simulation of a small number of test systems and machine-learning based prediction to find likely optimal system designs for a given target application. We demonstrate the effectiveness of our automated design methodology using 82 workload applications, generate SoC designs with up to 10 cores and 8 memory banks, and show that our classifier averages up to 92% of the optimal design performance across our applications.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127207224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Dynamic clustering for distinct parallel programming models on NoC-based MPSoCs 基于noc的mpsoc上不同并行编程模型的动态聚类

Network on Chip Architectures Pub Date : 2011-12-04 DOI: 10.1145/2076501.2076514

Gustavo Girão, Thiago Santini, F. Wagner

引用次数: 2

Partitioning and mapping on NoC-Based MPSoC: an energy consumption saving approach 基于noc的MPSoC的分区和映射:一种节能方法

Network on Chip Architectures Pub Date : 2011-12-04 DOI: 10.1145/2076501.2076512

Eduardo Antunes, A. Aguiar, S. J. Filho, M. Sartori, Fabiano Hessel, C. Marcon

引用次数: 9

Enhancing the security of time-division-multiplexing networks-on-chip through the use of multipath routing 通过使用多路径路由来增强片上时分多路网络的安全性

Network on Chip Architectures Pub Date : 2011-12-04 DOI: 10.1145/2076501.2076513

R. Stefan, K. Goossens

引用次数: 20

Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study 对比细粒度时钟域分区的多同步MPSoC设计风格:全高清视频播放案例研究

Network on Chip Architectures Pub Date : 2011-12-04 DOI: 10.1145/2076501.2076509

H. Tatenguem, D. Ludovici, Alessandro Strano, D. Bertozzi, H. Reinig

引用次数: 5

BOFAR: buffer occupancy factor based adaptive router for mesh NoCs 基于缓冲占用因子的网状noc自适应路由器

Network on Chip Architectures Pub Date : 2011-12-04 DOI: 10.1145/2076501.2076506

John Jose, J. Shankar, K. Mahathi, D. K. Kumar, M. Mutyam

{"title":"BOFAR: buffer occupancy factor based adaptive router for mesh NoCs","authors":"John Jose, J. Shankar, K. Mahathi, D. K. Kumar, M. Mutyam","doi":"10.1145/2076501.2076506","DOIUrl":"https://doi.org/10.1145/2076501.2076506","url":null,"abstract":"If the route computation operation in an adaptive router returns more than one output channels, the selection strategy chooses one from them based on the congestion metric used. The effectiveness of a selection strategy depends on what metric is used to identify congestion and how precisely that metric captures the actual congestion. The number of cycles a flit stays in a router is a direct indication of the contention level of the output port it desires to move out. We propose buffer Occupancy Factor based Adaptive Router (BOFAR), wherein the history of cycles spent by flits in buffers is used as the congestion metric. BOFAR outperforms the baseline architectures built on minimal odd-even adaptive router model with conventional selection strategies like count of free downstream virtual channels at reachable neighbors, and fluidity of buffers in downstream neighbors. Our experiments on 4x4 mesh NoC with various synthetic traffic patterns show that BOFAR exceeds the performance of best baseline adaptive router with 21% average and 78% maximum latency reduction at saturation load. The reduced average packet latency, increased buffer fluidity fairness, and increased saturation point of BOFAR with minimal overhead in area, power, and wiring makes it a promising alternative to existing adaptive routers in mesh NoCs.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127411198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10