Variability-tolerant NoC link design

In this paper we propose a model for the design of Networks-on-Chip (NoC) links that takes into considerations the systematic and random effects of process variability. The model predicts the delay variations of each NoC link in a floor-plan. Delay variations are used to modify the link design parameters, like the optimal number of buffered sections and their gains, to meet the delay constraints in a more variability-tolerant way. The proposed technique is tested using test cases of 4x4 meshes at 65 nm, 45nm, 32nm, and 22 nm technologies. Results show that the delay variations approach 10% of the total link delay and the total power cost using our technique is up to 33% compared to the nominal delay and power values in the absence of random and systematic variations effects. Yet our methodology has a lower power cost compared to the worst-case design, saving up to 28% of the total power consumption in the test case of the 4x4 mesh at 45 nm.