{"title":"Millimeter (mm)-wave wireless NoC as interconnection backbone for multicore chips: promises and challenges","authors":"P. Pande","doi":"10.1145/2536522.2536524","DOIUrl":null,"url":null,"abstract":"The continuing progress and integration levels in silicon technologies make complete end-user systems on a single chip possible. This massive level of integration makes modern multi-core chips all pervasive in domains ranging from weather forecasting, astronomical data analysis, and biological applications to consumer electronics and smart phones. NoCs have emerged as communication backbones to enable a high degree of integration in multi-core SoCs. Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multi-hop communications, wherein the data transfer between far-apart blocks causes high latency and power consumption. The latency, power consumption, and interconnect routing problems of NoCs can be simultaneously addressed by replacing multi-hop wired paths with high-bandwidth single-hop long-range wireless links. Recent investigations have established that the silicon integrated on-chip antenna operating in the millimeter wave range of a few tens to one hundred GHz is now a viable technology. Coupled with significant advances in mm-wave transceiver design, this opens up new opportunities for detailed investigations into wireless NoCs (WiNoCs). This talk will present methodologies and challenges for designing WiNoC architectures.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Network on Chip Architectures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2536522.2536524","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The continuing progress and integration levels in silicon technologies make complete end-user systems on a single chip possible. This massive level of integration makes modern multi-core chips all pervasive in domains ranging from weather forecasting, astronomical data analysis, and biological applications to consumer electronics and smart phones. NoCs have emerged as communication backbones to enable a high degree of integration in multi-core SoCs. Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multi-hop communications, wherein the data transfer between far-apart blocks causes high latency and power consumption. The latency, power consumption, and interconnect routing problems of NoCs can be simultaneously addressed by replacing multi-hop wired paths with high-bandwidth single-hop long-range wireless links. Recent investigations have established that the silicon integrated on-chip antenna operating in the millimeter wave range of a few tens to one hundred GHz is now a viable technology. Coupled with significant advances in mm-wave transceiver design, this opens up new opportunities for detailed investigations into wireless NoCs (WiNoCs). This talk will present methodologies and challenges for designing WiNoC architectures.