On heterogeneous network-on-chip design based on constraint programming

Core mapping and application scheduling problems coupled with routing schemes are essential design considerations for an efficient Network-on-Chip (NoC) design. This paper discusses heterogeneous NoC design from a Constraint Programming (CP) perspective using a two-stage solution. Given a Communication Task Graph (CTG) and subsequent task assignments for cores, cores are allocated to the best possible places on the chip in the first stage in order to minimize the overall communication cost among cores. We then solve the application scheduling problem in the second stage to determine the optimum core types from a list of technological alternatives and to minimize the makespan i.e. time to complete all tasks. As a design extension, surface area constraint can be introduced to the underlying problem. The paper reports results based on real benchmark datasets from the literature.