An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architecture

Mapping Intellectual Property (IP) cores onto a Network-on-Chip (NoC) architecture is an important phase of NoC design and the performance and energy consumption of the chip are the major issues that affect the design. In this paper, we analyze the preexistent mapping algorithms and present a new efficient energy and bandwidth aware topological mapping of IPs onto regular tile-based NoC architecture. The proposed algorithm has been implemented and evaluated for randomly generated benchmarks as well as real-life applications like Video Object Plane Decoder (VOPD) and Telecom. The experimental results have also been compared with existing mapping algorithms for the same set of benchmarks which clearly demonstrate significant reduction in maximum allocated bandwidth and energy for future NoC architectures with large number of IP cores. Further, there is a significant reduction in execution time of the proposed algorithm as compared to the other techniques.