{"title":"Evolution of the server processor/platform architecture and the critical role of interconnect and future challenges","authors":"G. Srinivasa","doi":"10.1145/1921249.1921251","DOIUrl":null,"url":null,"abstract":"Peering at the next decade, will explore the processor and platform architecture challenges, as to what areas are undergoing enormous changes, while surveying the learning over the past two decades.\n While exploring the next decade, will look at the processor internal interconnect evolution along with on chip resources starting with cache, memory controller and now being followed by IO integration vis-à-vis interchip multisocket interconnect at the platform level. Doing this, will outline the lessons learnt, what are the key challenges at macro and micro architecture level from the current perspective, where it is trending and some projections. I will describe the daily challenges and how we find sweet spots and surmount these in the interconnect area.\n The talk will emphasize the three key vectors architects wrestle with Power, Performance and Cost at the processor and platform level and the critical role played by interconnect. The interconnect matters in architecting server that include power, flexibility, bandwidth and latency at macro and micro level. Interconnect could make or break in the product continuity and is a matter of serious consequence. We will explore how these affect the picture at a bigger level be it rack or cluster or data center.\n With the current trend on Chip Multiprocessing mostly homogeneous that we have, will discuss the growth challenges that industry will face, what are the murky areas and state of SW and computing Industries key challenges. Will explore Heterogeneous computing, power and parallelization aspects and where we need a lot of research and focus.","PeriodicalId":344147,"journal":{"name":"Network on Chip Architectures","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Network on Chip Architectures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1921249.1921251","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Peering at the next decade, will explore the processor and platform architecture challenges, as to what areas are undergoing enormous changes, while surveying the learning over the past two decades.
While exploring the next decade, will look at the processor internal interconnect evolution along with on chip resources starting with cache, memory controller and now being followed by IO integration vis-à-vis interchip multisocket interconnect at the platform level. Doing this, will outline the lessons learnt, what are the key challenges at macro and micro architecture level from the current perspective, where it is trending and some projections. I will describe the daily challenges and how we find sweet spots and surmount these in the interconnect area.
The talk will emphasize the three key vectors architects wrestle with Power, Performance and Cost at the processor and platform level and the critical role played by interconnect. The interconnect matters in architecting server that include power, flexibility, bandwidth and latency at macro and micro level. Interconnect could make or break in the product continuity and is a matter of serious consequence. We will explore how these affect the picture at a bigger level be it rack or cluster or data center.
With the current trend on Chip Multiprocessing mostly homogeneous that we have, will discuss the growth challenges that industry will face, what are the murky areas and state of SW and computing Industries key challenges. Will explore Heterogeneous computing, power and parallelization aspects and where we need a lot of research and focus.