2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第5页

Routability Prediction using Deep Hierarchical Classification and Regression 基于深度层次分类和回归的可达性预测

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10136974

D. Kim, Jakang Lee, Seokhyeong Kang

引用次数: 1

VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations VE-FIDES:利用创新的指纹识别技术设计可信赖的供应链

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137026

Bernhard Lippmann, J. Hatsch, Stefan Seidl, Detlef Houdeau, Niranjana Papagudi Subrahmanyam, Daniel Schneider, Malek Safieh, Anne Passarelli, Aliza Maftun, M. Brunner, Tim Music, Michael Pehl, T. Siddiqui, R. Brederlow, Ulf Schlichtmann, Bjoern Driemeyer, M. Ortmanns, Robert Hesselbarth, Matthias Hiller

{"title":"VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations","authors":"Bernhard Lippmann, J. Hatsch, Stefan Seidl, Detlef Houdeau, Niranjana Papagudi Subrahmanyam, Daniel Schneider, Malek Safieh, Anne Passarelli, Aliza Maftun, M. Brunner, Tim Music, Michael Pehl, T. Siddiqui, R. Brederlow, Ulf Schlichtmann, Bjoern Driemeyer, M. Ortmanns, Robert Hesselbarth, Matthias Hiller","doi":"10.23919/DATE56975.2023.10137026","DOIUrl":"https://doi.org/10.23919/DATE56975.2023.10137026","url":null,"abstract":"The project VE-FIDES will contribute with a solution based on an innovative multi-level fingerprinting approach to secure electronics supply chains against the threats of malicious modification, piracy, and counterfeiting. Hardware-fingerprints are derived from minuscule, unavoidable process variations using the technology of Physical Unclonable Functions (PUFs). The derived fingerprints are processed to a system fingerprint enabling unique identification, not only of single components but also on PCB level. With the proposed concept, we show how the system fingerprint can enhance the trustworthiness of the overall system. For this purpose, the complete system including tiny sensors, a Secure Element and its interface to the application is considered in VE-FIDES. New insights into methodologies to derive component and system fingerprints are gained. These techniques for the verification of system integrity are complemented by methods for preventing reverse engineering. Two application scenarios are in the focus of VE-FIDES: Industrial control systems and an automotive use case are considered, giving insights to a wide spectrum of requirements for products built from components provided by international supply chains.","PeriodicalId":340349,"journal":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121544045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Timing Predictability for SOME/IP-based Service-Oriented Automotive In-Vehicle Networks 基于SOME/ ip的面向服务的汽车车载网络的时间可预测性

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137065

Enrico Fraccaroli, Prachi Joshi, Shengjie Xu, K. Shazzad, M. Jochim, S. Chakraborty

{"title":"Timing Predictability for SOME/IP-based Service-Oriented Automotive In-Vehicle Networks","authors":"Enrico Fraccaroli, Prachi Joshi, Shengjie Xu, K. Shazzad, M. Jochim, S. Chakraborty","doi":"10.23919/DATE56975.2023.10137065","DOIUrl":"https://doi.org/10.23919/DATE56975.2023.10137065","url":null,"abstract":"In-vehicle network architectures are evolving from a typical signal-based client-server paradigm to a service-oriented one, introducing flexibility for software updates and upgrades. While signal-based networks are static by nature, service-oriented ones can more easily evolve during and after the design phase. As a result, service-oriented protocols are becoming more prominent in automotive in-vehicle networks. While applications like infotainment are less sensitive to delays, others like sensing and control have more stringent timing and reliability requirements. Hence, wider adoption of service-oriented protocols requires addressing the timing analysis and predictability of such protocols, which is more challenging than in their signal-oriented counterparts. In service-oriented architectures, the discovery phase defines how clients find their required services. The time required to complete the discovery phase is an important parameter since it determines the readiness of a sub-system or even the vehicle. In this paper, we develop a formal timing analysis of the discovery phase of SOME/IP, which is an emerging service-oriented protocol being considered for adoption by several automotive Original Equipment Manufacturers (OEMs) and suppliers.","PeriodicalId":340349,"journal":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116150149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Process Variation Resilient Current-Domain Analog In Memory Computing 内存计算中的进程变化弹性电流域模拟

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137088

K.L.N. Prasad, Sai Shubham, Aditya Biswas, Joycee Mekie

{"title":"Process Variation Resilient Current-Domain Analog In Memory Computing","authors":"K.L.N. Prasad, Sai Shubham, Aditya Biswas, Joycee Mekie","doi":"10.23919/DATE56975.2023.10137088","DOIUrl":"https://doi.org/10.23919/DATE56975.2023.10137088","url":null,"abstract":"In-Memory Computing (IMC) has emerged as one of the energy-efficient solutions for data and compute-intensive machine learning applications. Analog IMC architectures have high throughput, but limited bit precision. Process variation further degrades the bit-precision. This work proposes an efficient way to track process variation and compensate for it to achieve high bit-resolution, which, to the best of our knowledge, is first such proposal. PV tracking is achieved by using an additional SRAM column and compensation by a non-conventional word-line driver. The proposed circuit can be augmented to any analog IMC architecture to make it resilient to process variations. To demonstrate the versatility of the proposal, we have implemented and analyzed 2-bit dot product operation in IMC architectures with six different SRAM cell configurations, and 2-bit, 4-bit, and 8-bit dot product on 6T SRAM IMC. For these, we report a reduction of $4times$ to $14times$ in the standard deviation of statistical variations in bit-line voltage for different SRAM cells, increase in the bit-resolution from 2 bits to 4 bits or 6 bits.","PeriodicalId":340349,"journal":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125627031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Securing a RISC-V architecture: A dynamic approach 保护RISC-V架构:一种动态方法

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10136972

S. Pillement, M. M. Real, J. Pottier, T. Nieddu, B. Gal, S. Faucou, Jean-Luc Béchennec, M. Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, D. G. Pérez, A. Sintzoff, J. R. Coulon

引用次数: 0

Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric Quo Vadis信号?用于晶体管级可编程结构编程后验证的自动方向性提取

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10136928

Apurva Jain, T. Broadfoot, Y. Makris, C. Sechen

{"title":"Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric","authors":"Apurva Jain, T. Broadfoot, Y. Makris, C. Sechen","doi":"10.23919/DATE56975.2023.10136928","DOIUrl":"https://doi.org/10.23919/DATE56975.2023.10136928","url":null,"abstract":"We discuss the challenges related with developing a post-programming verification solution for a TRAnsistor-level Programmable fabric (TRAP). Toward achieving high density, the TRAP architecture employs bidirectionally-operated pass transis-tors in the implementation of its logic and interconnect network. While it is possible to model such transistors through appropriate primitives of hardware description languages (HDL) to enable simulation-based validation, Logic Equivalence Checking (LEC) methods and tools do not support such primitives. As a result, formally verifying the functionality programmed by a given bit-stream on TRAP is not innately possible. To address this limitation, we introduce a method for automatically determining the signal flow direction through bidirectional pass transistors for a given bit-stream and subsequently converting the HDL describing the programmed fabric to consist only of unidirectional transistors. Thereby, commercial EDA tools can be used to check logic equivalence between the transistor-level HDL describing the programmed fabric and the post-synthesis gate-level netlist.","PeriodicalId":340349,"journal":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122594209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Real-Time Fully Unsupervised Domain Adaptation for Lane Detection in Autonomous Driving 基于实时全无监督域自适应的自动驾驶车道检测

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10136937

K. Bhardwaj, Zishen Wan, A. Raychowdhury, R. Goldhahn

引用次数: 1

COMPACT: Co-processor for Multi-mode Precision-adjustable Non-linear Activation Functions COMPACT:多模式精密可调非线性激活函数的协处理器

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137019

Wenhui Ou, Zhuoyu Wu, Z. Wang, Chao Chen, Yongkui Yang

{"title":"COMPACT: Co-processor for Multi-mode Precision-adjustable Non-linear Activation Functions","authors":"Wenhui Ou, Zhuoyu Wu, Z. Wang, Chao Chen, Yongkui Yang","doi":"10.23919/DATE56975.2023.10137019","DOIUrl":"https://doi.org/10.23919/DATE56975.2023.10137019","url":null,"abstract":"Non-linear activation functions imitating neuron behaviors are ubiquitous in machine learning algorithms for time series signals while also demonstrating significant gain in precision for conventional vision-based deep learning networks. State-of-the-art implementation of such functions on GPU-like devices incurs a large physical cost, whereas edge devices adopt either linear interpolation or simplified linear functions leading to degraded precision. In this work, we design COMPACT, a co-processor with adjustable precision for multiple non-linear activation functions including but not limited to exponent, sigmoid, tangent, logarithm, and mish. Benchmarking with state-of-the-arts, COMPACT achieves a 26% reduction in the absolute error on a 1.6x widen approximation range taking advantage of the triple decomposition technique inspired by Hajduk's formula of Padé approximation. A SIMD-ISA-based vector co-processor has been implemented on FPGA which leads to a 30% reduction in execution latency but the area overhead nearly remains the same with related designs. Furthermore, COMPACT is adjustable to 46% latency improvement when the maximum absolute error is tolerant to the order of 1E-3.","PeriodicalId":340349,"journal":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131478938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation 混合CMOS/MRAM Ascon硬件实现的安全性评估

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137126

Nathan Roussel, O. Potin, J. Dutertre, J. Rigaud

{"title":"Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation","authors":"Nathan Roussel, O. Potin, J. Dutertre, J. Rigaud","doi":"10.23919/DATE56975.2023.10137126","DOIUrl":"https://doi.org/10.23919/DATE56975.2023.10137126","url":null,"abstract":"As the number of IoT objects is growing fast, power consumption and security become a major concern in the design of integrated circuits. Lightweight Cryptography (LWC) algorithms aim to secure the communications of these connected objects at the lowest energy impact. To reduce the energy footprint of cryptographic primitives, several LWC hardware implementations embedding hybrid CMOS/MRAM-based cells have been investigated. These architectures use the non-volatile characteristic of MRAM to store data manipulated in the algorithm computation. We provide in this work a security evaluation of a hybrid CMOS/MRAM hardware implementation of the ASCON cipher, a finalist of the National Institute of Standards and Technology LWC contest. We focus on a simulation flow using the current EDA tools capable of carrying out power analysis for side-channel attacks, for the purpose of assessing potential weaknesses of MRAM hybridization. Differential Power Analysis (DPA) and Correlation Power Analysis (CPA) are conducted on the postroute and parasitic annoted netlist of the design. The results show that the hybrid implementation does not significantly lower the security feature compared to a reference CMOS implementation.","PeriodicalId":340349,"journal":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131588567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Safety-Guaranteed Framework for Neural-Network-Based Planners in Connected Vehicles under Communication Disturbance 通信干扰下基于神经网络的网联车辆规划器安全保障框架

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137184

K. Chang, Xiangguo Liu, Chung-Wei Lin, Chao Huang, Qi Zhu

引用次数: 3