S. Pillement, M. M. Real, J. Pottier, T. Nieddu, B. Gal, S. Faucou, Jean-Luc Béchennec, M. Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, D. G. Pérez, A. Sintzoff, J. R. Coulon
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Securing a RISC-V architecture: A dynamic approach
The SecureV (also known as SecV) project offers an innovative, open-source hardware, secure, and high-performance processor core based on the RISC-V ISA. The originality of the approach lies in the integration of a complete solution to increase security based on dynamic code transformation, covering 4 of the 5 NIST11National Institute of Standards and Technology functions of cybersecurity via monitoring (identify, detect), obfuscation (protect), and dynamic adaptation (react).
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