内存计算中的进程变化弹性电流域模拟

K.L.N. Prasad, Sai Shubham, Aditya Biswas, Joycee Mekie
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引用次数: 0

摘要

内存计算(IMC)已成为数据和计算密集型机器学习应用的节能解决方案之一。模拟IMC架构具有高吞吐量,但位精度有限。过程变化进一步降低了比特精度。这项工作提出了一种有效的方法来跟踪过程变化并对其进行补偿以实现高比特分辨率,据我们所知,这是第一个这样的建议。PV跟踪通过使用额外的SRAM列和非传统字行驱动器的补偿来实现。所提出的电路可以扩展到任何模拟IMC体系结构,使其能够适应工艺变化。为了证明该方案的通用性,我们在六种不同SRAM单元配置的IMC架构中实现并分析了2位点积运算,并在6T SRAM IMC上实现了2位、4位和8位点积运算。对于这些,我们报告了不同SRAM单元的位线电压统计变化的标准偏差减少了4倍到14倍,比特分辨率从2位增加到4位或6位。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Process Variation Resilient Current-Domain Analog In Memory Computing
In-Memory Computing (IMC) has emerged as one of the energy-efficient solutions for data and compute-intensive machine learning applications. Analog IMC architectures have high throughput, but limited bit precision. Process variation further degrades the bit-precision. This work proposes an efficient way to track process variation and compensate for it to achieve high bit-resolution, which, to the best of our knowledge, is first such proposal. PV tracking is achieved by using an additional SRAM column and compensation by a non-conventional word-line driver. The proposed circuit can be augmented to any analog IMC architecture to make it resilient to process variations. To demonstrate the versatility of the proposal, we have implemented and analyzed 2-bit dot product operation in IMC architectures with six different SRAM cell configurations, and 2-bit, 4-bit, and 8-bit dot product on 6T SRAM IMC. For these, we report a reduction of $4\times$ to $14\times$ in the standard deviation of statistical variations in bit-line voltage for different SRAM cells, increase in the bit-resolution from 2 bits to 4 bits or 6 bits.
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