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Proceedings of the 5th European Workshop on Low Temperature Electronics最新文献

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A 4.2 K readout channel in a standard 0.7 /spl mu/m CMOS process for a photoconductor array camera 用于光导体阵列相机的标准0.7 /spl mu/m CMOS工艺中的4.2 K读出通道
Proceedings of the 5th European Workshop on Low Temperature Electronics Pub Date : 2002-11-07 DOI: 10.1109/WOLTE.2002.1022481
Y. Creten, O. Charlier, P. Merken, J. Putzeys, C. van Hoof
{"title":"A 4.2 K readout channel in a standard 0.7 /spl mu/m CMOS process for a photoconductor array camera","authors":"Y. Creten, O. Charlier, P. Merken, J. Putzeys, C. van Hoof","doi":"10.1109/WOLTE.2002.1022481","DOIUrl":"https://doi.org/10.1109/WOLTE.2002.1022481","url":null,"abstract":"Abstrsct:The cryogenic design of a cold CMOS readout channel to be used in the Photoconductor Array Camera and Spectrometer (PACS) aboard the Herschel Space Observatory (HSO, formerly called FIRST) [I], is presented. Robust architectures and optimized sizing reduce the effect of cryogenic anomalities on the circuit. Simulation results and tests, both at room temperature and 4 K show a non-linearity < 2%, a hysteresis of <5mV and noise < 100nV/H~”~ @ 30Hz.","PeriodicalId":338080,"journal":{"name":"Proceedings of the 5th European Workshop on Low Temperature Electronics","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115937857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The impact of an external body-bias on the hot-carrier degradation of partially depleted SOI N-MOSFETs at cryogenic temperatures 外体偏置对低温下部分耗尽SOI n - mosfet热载流子降解的影响
Proceedings of the 5th European Workshop on Low Temperature Electronics Pub Date : 2002-11-07 DOI: 10.1109/WOLTE.2002.1022441
F. Dieudonné, J. Jomaah, C. Raynaud, F. Balestra
{"title":"The impact of an external body-bias on the hot-carrier degradation of partially depleted SOI N-MOSFETs at cryogenic temperatures","authors":"F. Dieudonné, J. Jomaah, C. Raynaud, F. Balestra","doi":"10.1109/WOLTE.2002.1022441","DOIUrl":"https://doi.org/10.1109/WOLTE.2002.1022441","url":null,"abstract":"Hot-carrier effects were studied in body-tied Partially Depleted SOI MOSFETs in a wide range of temperature, from 300 K down to 20 K. Devices under experimental tests were 0.25 μm long N-MOSFETs with a 10μm width. In this paper, the role of externally applied body-bias on the hot-carrier induced degradation is further investigated for five different temperatures. Our devices underwent accelerated electrical stress applying different negative body-biases as well as drain and front gate biases chosen to obtain reasonable stress duration. The variations of the main electrical parameters such as the maximal transconductance, the driving current or the threshold voltage are reported.","PeriodicalId":338080,"journal":{"name":"Proceedings of the 5th European Workshop on Low Temperature Electronics","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121183695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Mesoscopic transport characteristics of nano-scale SOI MOSFETs: coulomb blockade and localization 纳米SOI mosfet的介观输运特性:库仑阻滞和局域化
Proceedings of the 5th European Workshop on Low Temperature Electronics Pub Date : 2002-11-07 DOI: 10.1109/WOLTE.2002.1022457
Y. Omura, M. Yamamoto
{"title":"Mesoscopic transport characteristics of nano-scale SOI MOSFETs: coulomb blockade and localization","authors":"Y. Omura, M. Yamamoto","doi":"10.1109/WOLTE.2002.1022457","DOIUrl":"https://doi.org/10.1109/WOLTE.2002.1022457","url":null,"abstract":"This paper describes the transport characteristics, measured at 1.1 K, of 50-nm-channel SOI MOSFETs with a 6-nm-thick silicon layer. To verify electron localization, Fermi wavelength, periodic length of primary interface morphology, and ideal cyclotron radius are estimated theoretically. It is shown that non-periodic roughness may contribute to Anderson localization while the local periodic structure of the interface morphology is associated with Coulomb blockade.","PeriodicalId":338080,"journal":{"name":"Proceedings of the 5th European Workshop on Low Temperature Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128820120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigations on the low-power and low-frequency noise performance of pHEMT at 4.2 K pHEMT在4.2 K时的低功耗和低频噪声性能研究
Proceedings of the 5th European Workshop on Low Temperature Electronics Pub Date : 2002-11-07 DOI: 10.1109/WOLTE.2002.1022463
T. Lucas, Y. Jin
{"title":"Investigations on the low-power and low-frequency noise performance of pHEMT at 4.2 K","authors":"T. Lucas, Y. Jin","doi":"10.1109/WOLTE.2002.1022463","DOIUrl":"https://doi.org/10.1109/WOLTE.2002.1022463","url":null,"abstract":"Pseudomorphic GaAs HEMTs with a gate length of 1μm have been realized and characterized at 4.2K. For the device with a gate width of 4mm, a gate leakage current less than 1pA and a total input capacitance lower than 10pF have been obtained for any practical bias conditions. The channel resistance can be modified more than 10 9 times with a gate bias variation less than a half volt. An intrinsic voltage gain higher than 10 can be reached with a power dissipation equal to or less than 0.15mW. Under this power supply condition, equivalent input noise voltages of 8.4, 3.2 and down to 1.3nV/√Hz can be obtained at frequencies of 1, 10 and 100kHz respectively. This noise voltage has been studied as a function of the drain current. Finally, the experimental results of this work have shown that the device's noise voltage can be linked to its DC parameters.","PeriodicalId":338080,"journal":{"name":"Proceedings of the 5th European Workshop on Low Temperature Electronics","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131057867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
RSFQ: The fastest digital technology RSFQ:最快的数字技术
Proceedings of the 5th European Workshop on Low Temperature Electronics Pub Date : 2002-11-07 DOI: 10.1051/JP420020057
K. Likharev
{"title":"RSFQ: The fastest digital technology","authors":"K. Likharev","doi":"10.1051/JP420020057","DOIUrl":"https://doi.org/10.1051/JP420020057","url":null,"abstract":"This paper deals with the recent progress in the development of Rapid Single-Flux-Quantum (RSFQ) digital technology based on macroscopic quantum effects in superconductors. Elementary cells of this logic family store and process digital bits in the form of single quanta of magnetic flux, while the data exchange between the cells is provided with picosecond pulses transferred along superconductor microstrip lines with a speed approaching the speed of light. RSFQ devices combine a unique set of","PeriodicalId":338080,"journal":{"name":"Proceedings of the 5th European Workshop on Low Temperature Electronics","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131098105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A relationship between 1/f noise and DC parameters in the pHEMT at 4.2 K 4.2 K时pHEMT中1/f噪声与直流参数的关系
Proceedings of the 5th European Workshop on Low Temperature Electronics Pub Date : 2002-11-07 DOI: 10.1109/WOLTE.2002.1022461
T. Lucas, Y. Jin
{"title":"A relationship between 1/f noise and DC parameters in the pHEMT at 4.2 K","authors":"T. Lucas, Y. Jin","doi":"10.1109/WOLTE.2002.1022461","DOIUrl":"https://doi.org/10.1109/WOLTE.2002.1022461","url":null,"abstract":"According to the Hooge empirical 1/f formula, a linear relationship between the squared equivalent input 1/f noise voltage and the ratio of drain current over squared transconductance has been developed. Low-power and low-frequency noise pHEMTs with gate lengths of 4 and 1 μm have been fabricated and characterized at 4.2K. The obtained noise and DC data are in good agreement with this developed expression when drain biases are fixed in both of quasi-linear and saturation regimes. This relationship provides the possibilities to evaluate the device noise level by its DC parameters and to determine the Hooge coefficient by directly measurable parameters.","PeriodicalId":338080,"journal":{"name":"Proceedings of the 5th European Workshop on Low Temperature Electronics","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132954380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Electronics for deep space cryogenic applications 深空低温应用电子器件
Proceedings of the 5th European Workshop on Low Temperature Electronics Pub Date : 2002-11-07 DOI: 10.1109/WOLTE.2002.1022482
R. Patterson, A. Hammoud, J. Dickman, S. Gerber, M. Elbuluk, E. Overton
{"title":"Electronics for deep space cryogenic applications","authors":"R. Patterson, A. Hammoud, J. Dickman, S. Gerber, M. Elbuluk, E. Overton","doi":"10.1109/WOLTE.2002.1022482","DOIUrl":"https://doi.org/10.1109/WOLTE.2002.1022482","url":null,"abstract":"Deep space probes and planetary exploration missions require electrical power management and control systems that are capable of efficient and reliable operation in very cold temperature environments. Typically, in deep space probes, heating elements are used to keep the spacecraft electronics near room temperature. The utilization of power electronics designed for and operated at low temperature will contribute to increasing efficiency and improving reliability of space power systems. At NASA Glenn Research Center, commercial-off-the-shelf devices as well as developed components are being investigated for potential use at low temperatures. These devices include semiconductor switching devices, magnetics, and capacitors. Integrated circuits such as digital-to-analog and analog-to-digital converters, DC/DC converters, operational amplifiers, and oscillators are also being evaluated. In this paper, results will be presented for selected analog-to-digital converters, oscillators, DC/DC converters, and pulse width modulation (PWM) controllers.","PeriodicalId":338080,"journal":{"name":"Proceedings of the 5th European Workshop on Low Temperature Electronics","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125411733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Temperature scaling of nanoscale silicon MOSFETs 纳米硅mosfet的温度缩放
Proceedings of the 5th European Workshop on Low Temperature Electronics Pub Date : 2002-11-07 DOI: 10.1109/WOLTE.2002.1022443
V. Sverdlov, Y. Naveh, K. Likharev
{"title":"Temperature scaling of nanoscale silicon MOSFETs","authors":"V. Sverdlov, Y. Naveh, K. Likharev","doi":"10.1109/WOLTE.2002.1022443","DOIUrl":"https://doi.org/10.1109/WOLTE.2002.1022443","url":null,"abstract":"We have combined a 1D model of double-gate MOSFETs with ultrathin intrinsic channel, with a simple model of power consumption in digital integrated circuits, to calculate the temperature dependence of the minimum total (static + dynamic) power P and the optimal power supply voltage V DD . The results are strongly dependent on the circuit speed assumptions. If the current trend of speed scaling with the critical size reduction is sustained, both P and V DD saturate as soon as T is decreased below 100 K. On the other hand, if the high speed condition is removed, transistors may operate in the subthreshold region and minimum value of P scales as T 2 while the optimum value of V DD drops as T. This reduction is, however, limited by thermal fluctuations, leading to a different scaling, V DD T 1/2 and P T 1 , for low temperatures and/or large circuit densities. Because of this limitation, deep cooling of CMOS circuits may make sense only in very special cases.","PeriodicalId":338080,"journal":{"name":"Proceedings of the 5th European Workshop on Low Temperature Electronics","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122276204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Investigation of radiation hardness of SIS junctions for space borne radio astronomy 星载射电天文SIS节点辐射硬度研究
Proceedings of the 5th European Workshop on Low Temperature Electronics Pub Date : 2002-05-01 DOI: 10.1109/WOLTE.2002.1022475
I. Péron, G. Faury, Y. Delorme, F. Dauplay, B. Lecomte, M. SaIez, K. Schuster
{"title":"Investigation of radiation hardness of SIS junctions for space borne radio astronomy","authors":"I. Péron, G. Faury, Y. Delorme, F. Dauplay, B. Lecomte, M. SaIez, K. Schuster","doi":"10.1109/WOLTE.2002.1022475","DOIUrl":"https://doi.org/10.1109/WOLTE.2002.1022475","url":null,"abstract":"Submillimeter astronomy with SIS (Superconductor-Insulator-Superconductor) mixers in space offer access to new wavelength windows and unsurpassed sensitivity. However little is known about the behavior of these devices in space. The Heterodyne Instrument (HIFI) aboard ESA's cornerstone Herschel Space Observatory (formely FIRST) satellite, scheduled for launch in 2007, will be among the first instrument using SIS technology in space. Within this context it is important to study possible radiation damage effects in SIS tunnel junctions. The particular devices used for HERSCHEL-HIFI-Band 1 (480-640 GHz) were fabricated with a new process based on negative resist E-beam lithography and very high current densities (15 kA/cm 2 ). In this paper, we report on radiation hardness tests with 10 MeV protons on the described high current density Nb/Al-AlOx/Nb junctions.","PeriodicalId":338080,"journal":{"name":"Proceedings of the 5th European Workshop on Low Temperature Electronics","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131244902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Demonstration of an 4.2 K analog switch matrix in a standard 0.7 /spl mu/ CMOS process 在标准的0.7 /spl mu/ CMOS工艺中演示4.2 K模拟开关矩阵
Proceedings of the 5th European Workshop on Low Temperature Electronics Pub Date : 2002-05-01 DOI: 10.1109/WOLTE.2002.1022483
Y. Creten, J. De Hert, O. Charlier, P. Merken, J. Putzeys, C. Van Hoof
{"title":"Demonstration of an 4.2 K analog switch matrix in a standard 0.7 /spl mu/ CMOS process","authors":"Y. Creten, J. De Hert, O. Charlier, P. Merken, J. Putzeys, C. Van Hoof","doi":"10.1109/WOLTE.2002.1022483","DOIUrl":"https://doi.org/10.1109/WOLTE.2002.1022483","url":null,"abstract":"In this extended abstract a 4x4 Field Programmable Analogue Array or switch matrix is presented. Design and preliminary data will be discussed.","PeriodicalId":338080,"journal":{"name":"Proceedings of the 5th European Workshop on Low Temperature Electronics","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132579640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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