2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)最新文献_第3页

Hardware Accelerated FrodoKEM on RISC-V 基于RISC-V的硬件加速FrodoKEM

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770148

Patrick Karl, Tim Fritzmann, G. Sigl

引用次数: 1

Towards Polynomial Formal Verification of Complex Arithmetic Circuits 复杂算术电路的多项式形式验证研究

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770156

R. Drechsler, Alireza Mahzoon, Mehran Goli

{"title":"Towards Polynomial Formal Verification of Complex Arithmetic Circuits","authors":"R. Drechsler, Alireza Mahzoon, Mehran Goli","doi":"10.1109/ddecs54261.2022.9770156","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770156","url":null,"abstract":"With the growing demands for highly area-efficient, delay-optimized, and low-power designs, the complexity of digital circuits is increasing as well. Especially, a wide variety of arithmetic circuits, including different types of adders, multipliers, and dividers have been proposed to meet the demands in applications such as cryptography and Artificial Intelligence (AI). Some of these arithmetic circuits have highly parallel architectures and contain millions of gates; as a result, they are extremely error-prone. In the last 30 years, several formal verification methods have been proposed to verify arithmetic circuits. These methods report very good results when it comes to the verification of adders and structurally simple multipliers. Moreover, their space and time complexities are polynomial, i.e, they are scalable. However, when it comes to the verification of structurally complex multipliers, the story is different.In this paper, we investigate the space and time complexity of verifying a structurally complex multiplier using a word-level verification method. We prove that the space and time complexity is always exponential. Then, we introduce a new verification strategy that takes advantage of several verification engines. We show that the polynomial formal verification of the complex multiplier becomes possible if the correctness of each stage is verified using the proper verification method. Our verification strategy can be applied to other complex digital circuits.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130375021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Functional Verification of Arithmetic Circuits: Survey of Formal Methods 算术电路的功能验证:形式化方法综述

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770161

M. Ciesielski, Atif Yasin, Jiteshri Dasari

引用次数: 0

Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770169

Alessandro Veronesi, Francesco Dall'Occo, D. Bertozzi, M. Favalli, M. Krstic

引用次数: 3

Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions RISC-V指令集扩展的虚拟样机驱动设计、实现与评估

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770108

Milan Funck, V. Herdt, R. Drechsler

引用次数: 3

Selective Hardening of Critical Neurons in Deep Neural Networks 深度神经网络中关键神经元的选择性硬化

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770168

A. Ruospo, G. Gavarini, Ilaria Bragaglia, Marcello Traiola, A. Bosio, Ernesto Sánchez

{"title":"Selective Hardening of Critical Neurons in Deep Neural Networks","authors":"A. Ruospo, G. Gavarini, Ilaria Bragaglia, Marcello Traiola, A. Bosio, Ernesto Sánchez","doi":"10.1109/ddecs54261.2022.9770168","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770168","url":null,"abstract":"In the literature, it is argued that Deep Neural Networks (DNNs) possess a certain degree of robustness mainly for two reasons: their distributed and parallel architecture, and their redundancy introduced due to over provisioning. Indeed, they are made, as a matter of fact, of more neurons with respect to the minimal number required to perform the computations. It means that they could withstand errors in a bounded number of neurons and continue to function properly. However, it is also known that different neurons in DNNs have divergent fault tolerance capabilities. Neurons that contribute the least to the final prediction accuracy are less sensitive to errors. Conversely, the neurons that contribute most are considered critical because errors within them could seriously compromise the correct functionality of the DNN. This paper presents a software methodology based on a Triple Modular Redundancy technique, which aims at improving the overall reliability of the DNN, by selectively protecting a reduced set of critical neurons. Our findings indicate that the robustness of the DNNs can be enhanced, clearly, at the cost of a larger memory footprint and a small increase in the total execution time. The trade-offs as well as the improvements are discussed in the work by exploiting two DNN architectures: ResNet and DenseNet trained and tested on CIFAR-10.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125648338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking 用统计模型检验的方法分析AxC系统的动态方面

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770166

Josef Strnadel

{"title":"Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking","authors":"Josef Strnadel","doi":"10.1109/ddecs54261.2022.9770166","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770166","url":null,"abstract":"Many researchers shown that approximate circuits are able to provide a new perspective on the development of electronic systems. Mostly, they tried to find an optimal trade-off between the approximation error and resource savings for predefined applications. However, they used to concentrate mainly on design aspects regarding relaxed functional requirements, but neglected aspects like timing, sequential/asynchronous nature of circuits, uncertainty due to process/parameter variations, excessively high operating frequencies or low voltages. This paper aims to take a step ahead by moving towards the verification of dynamic properties of systems based on approximate circuits, with a focus on sequential/asynchronous circuits and uncertainty. First, the paper presents our approach to modeling approximate systems by means of stochastic hybrid timed automata. Then, it shows the principle/advantage of verifying properties of modeled systems by the so-called statistical model checking technique. Further, it presents a framework that takes at its input the model of an accurate system, its timing and other requirements and expected properties, information about basic building blocks and acceptable cost/quality trade-off to produce an approximated system that meets the requirements maximally and satisfies the properties. Finally, the paper evaluates our approach and outlines future research perspectives.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132807780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On SAT-Based Model Checking of Speed-Independent Circuits 基于sat的速度无关电路的模型检验

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770165

F. Huemer, Robert Najvirt, A. Steininger

{"title":"On SAT-Based Model Checking of Speed-Independent Circuits","authors":"F. Huemer, Robert Najvirt, A. Steininger","doi":"10.1109/ddecs54261.2022.9770165","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770165","url":null,"abstract":"Formal verification plays an important role in the quality assurance of digital circuits. Apart from the now standard equivalence checking between design steps, functional correctness can be proven with model checking. In one approach, a Boolean satisfiability (SAT) problem describing the circuit’s implementation and expected properties is generated for each of a bounded number of time steps and fed to a SAT solver. In synchronous circuits, the time steps correspond to cycles of the global clock. The execution of asynchronous, specifically speed-independent (SI) circuits, however, relies on local handshakes instead of a global time reference. This absence of a global clock requires a different approach for choosing time steps for the SAT problem.This paper presents how bounded, SAT-based model checking can be used on SI asynchronous circuits. We aim to give a general and accessible introduction to this topic, highlight the inherent computational complexity and show that setting up a basic model checker for SI circuits is possible with quite simple means, without any reliance on (expensive) commercial tools. For our reference implementation used in the provided examples we use the open source Z3 solver.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133711943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DDECS 2022 Cover Page DDECS 2022封面

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770158

引用次数: 0

Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks 针对故障注入攻击的硬件指令重放的处理器扩展

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770170

Noura Ait Manssour, Vianney Lapôtre, G. Gogniat, A. Tisserand

引用次数: 2