Alessandro Veronesi, Francesco Dall'Occo, D. Bertozzi, M. Favalli, M. Krstic
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引用次数: 3

摘要

然而,他们面临着保持软件可见变量和错误微架构状态之间一致性的挑战。这项工作的目标是确定一个合适的加速器建模,在不使仿真引擎过载的情况下进行分析。为了实现这一目标,本文探讨了不同的加速器建模策略,这些策略具有提高硬件可见性水平的特点。我们的研究结果表明,微妙的微架构细节通常被竞争方法所忽视,在确定加速器可靠性方面发挥着相关作用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study
Deep learning accelerator models described with software imperative languages are frequently used for their large-scale reliability analysis in order to overcome the prohibitive simulation times of logic-level and RTL models. However, they are faced with the challenge of preserving consistency between software-visible variables and faulty microarchitectural states. The goal of this work is to determine a suitable accelerator modelling that enables analysis without overloading the simulation engine. Toward this goal, the paper explores different accelerator modelling strategies featuring increasing levels of hardware visibility. They are compared in their capability to gain insights into the reliability of the multiply-and-accumulate (MAC) pipeline of an industry-standard deep learning accelerator from NVIDIA. Our results show that subtle microarchitectural details that are typically overlooked by competing approaches play a relevant role in determining accelerator reliability.
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