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2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)最新文献

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Stochastic Computing Architectures for Lightweight LSTM Neural Networks 轻量级LSTM神经网络的随机计算体系结构
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770167
Roshwin Sengupta, I. Polian, J. Hayes
{"title":"Stochastic Computing Architectures for Lightweight LSTM Neural Networks","authors":"Roshwin Sengupta, I. Polian, J. Hayes","doi":"10.1109/ddecs54261.2022.9770167","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770167","url":null,"abstract":"For emerging edge and near-sensor systems to perform hard classification tasks locally, they must avoid costly communication with the cloud. This requires the use of compact classifiers such as recurrent neural networks of the long short term memory (LSTM) type, as well as a low-area hardware technology such as stochastic computing (SC). We study the benefits and costs of applying SC to LSTM design. We consider a design space spanned by fully binary (non-stochastic), fully stochastic, and several hybrid (mixed) LSTM architectures, and design and simulate examples of each. Using standard classification benchmarks, we show that area and power can be reduced up to 47% and 86% respectively with little or no impact on classification accuracy. We demonstrate that fully stochastic LSTMs can deliver acceptable accuracy despite accumulated errors. Our results also suggest that ReLU is preferable to tanh as an activation function in stochastic LSTMs","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115100232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Programmable logic elements using multigate ambipolar transistors 使用多门双极晶体管的可编程逻辑元件
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770137
Ashton Snelgrove, P. Gaillardon
{"title":"Programmable logic elements using multigate ambipolar transistors","authors":"Ashton Snelgrove, P. Gaillardon","doi":"10.1109/ddecs54261.2022.9770137","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770137","url":null,"abstract":"We propose a general purpose logic element with eight variations, built using multigate ambipolar transistors, sufficiently capable to replace LUTs in FPGAs. We simulate the new logic element using a 10nm silicon-nanowire three-input-gate transistor model, and compare the proposed element to lookup tables and reconfigurable logic elements from the literature implemented using the same technology model. We compare the different elements for delay, power, and number of transistors, specifically accounting for the cost of configuration storage. Compared to an equivalent LUT, the logic element variation with the most available boolean functions uses 90% of the transistors, with a penalty in delay of 102%, and improved dynamic and static power of 97% and 91%, respectively. The smallest variation uses 42% of the transistors, with improved delay of 76%, and improved dynamic and static power of 43% and 43%, respectively.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114434499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression 基于线性回归的RISC-V处理器嵌入式软件早期性能评估
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770144
Weiyan Zhang, Mehran Goli, R. Drechsler
{"title":"Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression","authors":"Weiyan Zhang, Mehran Goli, R. Drechsler","doi":"10.1109/ddecs54261.2022.9770144","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770144","url":null,"abstract":"RISC-V-based embedded systems are becoming more and more popular in recent years. Performance estimation of embedded software at an early stage of the design process plays an important role in efficient design space exploration and reducing time-to-market constraints. Although several cycle-accurate RISC-V simulators at different levels of abstraction have been proposed, they have an inherently high cost, both for the development of the simulation setting and for obtaining the software performance in terms of the number of cycles through simulation. This results in a significant burden on designers to perform design space exploration.In this paper, we present a novel ML-based approach, enabling designers to fast and accurately estimate the performance of a given embedded software implemented on the RISC-V processor at the early stage of the design process. The proposed approach is evaluated against a real-world cycle-accurate RISC-V Virtual Prototype (VP) using a set of standard benchmarks. Our experiments demonstrate that our approach allows obtaining highly-accurate performance estimation results in a short execution time. In comparison to the cycle-accurate RISC-V VP model, the proposed approach achieves up to more than 5 x faster simulation speed and less than 2.5% prediction error on average.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114577897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Exploiting PUF Variation to Detect Fault Injection Attacks 利用PUF变异检测故障注入攻击
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770154
Troya Çağıl Köylü, Luíza C. Garaffa, C. Reinbrecht, Mahdi Zahedi, S. Hamdioui, M. Taouil
{"title":"Exploiting PUF Variation to Detect Fault Injection Attacks","authors":"Troya Çağıl Köylü, Luíza C. Garaffa, C. Reinbrecht, Mahdi Zahedi, S. Hamdioui, M. Taouil","doi":"10.1109/ddecs54261.2022.9770154","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770154","url":null,"abstract":"The massive deployment of Internet of Things (IoT) devices makes them vulnerable against physical tampering attacks, such as fault injection. These kind of hardware attacks are very popular as they typically do not require complex equipment or high expertise. Hence, it is important that IoT devices are protected against them. In this work, we present a novel fault injection attack detector with high flexibility and low overhead. Our solution is based on the reuse of a security primitive used in many IoT devices, i.e., ring oscillator (RO) physically unclonable function (PUF). Our results show that we obtain a high detection effectiveness and no false alarms against most popular fault injection attacks based on voltage and clock manipulations.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115111067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Design Space Exploration Framework for Memristor-Based Crossbar Architecture 一种基于忆阻器的跨栅结构设计空间探索框架
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770145
M. Barbareschi, A. Bosio, Ian O’Connor, P. Fiser, Marcello Traiola
{"title":"A Design Space Exploration Framework for Memristor-Based Crossbar Architecture","authors":"M. Barbareschi, A. Bosio, Ian O’Connor, P. Fiser, Marcello Traiola","doi":"10.1109/ddecs54261.2022.9770145","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770145","url":null,"abstract":"In the literature, there are few studies describing how to implement Boolean logic functions as a memristor-based crossbar architecture and some solutions have been actually proposed targeting back-end synthesis. However, there is a lack of methodologies and tools for the synthesis automation. The main goal of this paper is to perform a Design Space Exploration (DSE) in order to analyze and compare the impact of the most used optimization algorithms on a memristor-based crossbar architecture. The results carried out on 102 circuits lead us to identify the best optimization approach, in terms of area/energy/delay. The presented results can also be considered as a reference (benchmarking) for comparing future work.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129480743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On-Chip Current Sensing Approaches for DC-DC Converters DC-DC变换器的片上电流传感方法
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770112
R. Ravasz, A. Hudec, D. Arbet, V. Stopjaková
{"title":"On-Chip Current Sensing Approaches for DC-DC Converters","authors":"R. Ravasz, A. Hudec, D. Arbet, V. Stopjaková","doi":"10.1109/ddecs54261.2022.9770112","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770112","url":null,"abstract":"In this paper, methods suitable for sensing the output load current (or current consumption) of analog circuits were studied and analyzed. The main focus was paid on approaches that can be implemented on a chip. The proposed approach for sensing the output current of a DC-DC converter is based on measuring the slope of a voltage sensed by an output bypass capacitor. Such an indirect sensing approach shows better efficiency than a common shunt resistor sensing method. The presented approach was used in a flyback type DC-DC converter. The simulated results prove better voltage conversion efficiency using the proposed indirect measurement approach.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128988683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analyzing Multilevel Stochastic Circuits using Correlation Matrices 用相关矩阵分析多水平随机电路
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770115
Owen Hoffend, J. Hayes
{"title":"Analyzing Multilevel Stochastic Circuits using Correlation Matrices","authors":"Owen Hoffend, J. Hayes","doi":"10.1109/ddecs54261.2022.9770115","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770115","url":null,"abstract":"Stochastic computing (SC) is a digital design paradigm that foregoes the conventional binary encoding in favor of pseudo-random bitstreams. Stochastic circuits operate on the probability values of bitstreams, and often achieve low power, low area, and fault-tolerant computation. Most SC designs rely on the input bitstreams being independent or uncorrelated to obtain the best results. However, circuits have also been proposed that exploit deliberately correlated bitstreams to improve area or accuracy. In such cases, different sub-circuits may have different correlation requirements. A major barrier to multi-layer or hierarchical stochastic circuit design has been understanding how correlation propagates from a circuit’s inputs to its outputs while meeting the correlation requirements for all its sub-circuits. In this paper, we introduce correlation matrices and extensions to probability transfer matrix (PTM) algebra to analyze complex correlation behavior, thereby alleviating the need for computationally intensive bit-wise simulation. We apply our new correlation analysis to two multi-layer SC image processing and neural network circuits and show that it helps designers to systematically reduce correlation error.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130726085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors 微处理器中针对硬件木马的软件混淆优化
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770162
Luca Cassano, Elia Lazzeri, N. Litovchenko, G. D. Natale
{"title":"On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors","authors":"Luca Cassano, Elia Lazzeri, N. Litovchenko, G. D. Natale","doi":"10.1109/ddecs54261.2022.9770162","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770162","url":null,"abstract":"The quest of low production cost and short time-to-market, as well as the complexity of modern integrated circuits pushed towards a globalization of the supply chain of silicon devices. Such production paradigm raised a number of security threats among which Hardware Trojan Horses (HTHs), that became a serious issue not only for academy but also for industry in the very last years. Indeed, it has been demonstrated that HTHs can be inserted into microprocessors allowing the attacker to run malicious software, to acquire root privileges or to steal secret information. In this paper we present the use of software obfuscation to protect systems against HTHs that aim at stealing information from the microprocessor while it is executing a program. Moreover, we present a Genetic Algorithm-based approach to optimize such anti-HTH methodology by maximizing the obtained obfuscation while minimizing the introduced overhead. We proved the effectiveness and efficiency of the proposed methodology on the Ariane 64bit RISC-V microprocessor running a set of MiBench benchmarks and cryptographic programs.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128804424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
DDECS 2022 Organizing Committee DDECS 2022组委会
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770149
{"title":"DDECS 2022 Organizing Committee","authors":"","doi":"10.1109/ddecs54261.2022.9770149","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770149","url":null,"abstract":"","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128951200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Correlation Power Analysis of SipHash SipHash相关功率分析
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-04-06 DOI: 10.1109/ddecs54261.2022.9770139
Matús Oleksák, Vojtech Miskovský
{"title":"Correlation Power Analysis of SipHash","authors":"Matús Oleksák, Vojtech Miskovský","doi":"10.1109/ddecs54261.2022.9770139","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770139","url":null,"abstract":"SipHash is ARX-based pseudorandom function optimized for short inputs. It was developed as a hash table lookup function, but it is also used for MAC generation. At the time of writing, there was no side-channel attack on SipHash known to us. This work is about application of CPA attack on SipHash. Attack was performed on ChipWhisperer CW308 UFO Board with STM32F0 target. Approximately 800 power traces were needed for succesful attack. Leakage information from XOR was used to attack cipher key. The main contribution of this work is power model of binary addition including carry propagation.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130381050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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