2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)最新文献

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ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators 硬件加速器的算术电路生成器

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-03-09 DOI: 10.1109/DDECS54261.2022.9770152

Jan Klhufek, Vojtěch Mrázek

{"title":"ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators","authors":"Jan Klhufek, Vojtěch Mrázek","doi":"10.1109/DDECS54261.2022.9770152","DOIUrl":"https://doi.org/10.1109/DDECS54261.2022.9770152","url":null,"abstract":"Generators of arithmetic circuits can automatically deliver various implementations of arithmetic circuits that show different tradeoffs between the key circuit parameters (delay, area, power consumption). However, existing (freely-)available generators are limited if more complex circuits with a hierarchical structure and additional architecture optimization are requested. Furthermore, they support only a few output formats. In order to overcome the above-mentioned limitations, we developed a new generator of arithmetic circuits called ArithsGen. ArithsGen can generate specific architectures of signed and unsigned adders and multipliers using basic building elements such as wires and gates. Compared to existing generators, the user can, for example, specify the type of adders used in multipliers. The tool supports various outputs formats (Verilog, BLIF, C/C++, or integer netlists). ArithsGen was evaluated in the synthesis and optimization of generic customizable accurate and approximate adders and multipliers. Furthermore, we used the circuits generated by ArithsGen as seeds for a tool developed to automatically create approximate implementations of arithmetic circuits. We show that different initial circuits (generated by ArithsGen) significantly impact the properties of these approximate implementations. The tool is available online at https://github.com/ehw-fit/ariths-gen.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126304618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Hardware Obfuscation of Digital FIR Filters 数字FIR滤波器的硬件混淆

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Pub Date : 2022-02-21 DOI: 10.1109/ddecs54261.2022.9770141

L. Aksoy, Alexander Hepp, Johanna Baehr, S. Pagliarini

{"title":"Hardware Obfuscation of Digital FIR Filters","authors":"L. Aksoy, Alexander Hepp, Johanna Baehr, S. Pagliarini","doi":"10.1109/ddecs54261.2022.9770141","DOIUrl":"https://doi.org/10.1109/ddecs54261.2022.9770141","url":null,"abstract":"A finite impulse response (FIR) filter is a ubiquitous block in digital signal processing applications. Its characteristics are determined by its coefficients, which are the intellectual property (IP) for its designer. However, in a hardware efficient realization, its coefficients become vulnerable to reverse engineering. This paper presents a filter design technique that can protect this IP, taking into account hardware complexity and ensuring that the filter behaves as specified only when a secret key is provided. To do so, coefficients are hidden among decoys, which are selected beyond possible values of coefficients using three alternative methods. As an attack scenario, an adversary at an untrusted foundry is considered. A reverse engineering technique is developed to find the chosen decoy selection method and explore the potential leakage of coefficients through decoys. An oracle-less attack is also used to find the secret key. Experimental results show that the proposed technique can lead to filter designs with competitive hardware complexity and higher resiliency to attacks with respect to previously proposed methods.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115285211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

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