{"title":"使用多门双极晶体管的可编程逻辑元件","authors":"Ashton Snelgrove, P. Gaillardon","doi":"10.1109/ddecs54261.2022.9770137","DOIUrl":null,"url":null,"abstract":"We propose a general purpose logic element with eight variations, built using multigate ambipolar transistors, sufficiently capable to replace LUTs in FPGAs. We simulate the new logic element using a 10nm silicon-nanowire three-input-gate transistor model, and compare the proposed element to lookup tables and reconfigurable logic elements from the literature implemented using the same technology model. We compare the different elements for delay, power, and number of transistors, specifically accounting for the cost of configuration storage. Compared to an equivalent LUT, the logic element variation with the most available boolean functions uses 90% of the transistors, with a penalty in delay of 102%, and improved dynamic and static power of 97% and 91%, respectively. The smallest variation uses 42% of the transistors, with improved delay of 76%, and improved dynamic and static power of 43% and 43%, respectively.","PeriodicalId":334461,"journal":{"name":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Programmable logic elements using multigate ambipolar transistors\",\"authors\":\"Ashton Snelgrove, P. Gaillardon\",\"doi\":\"10.1109/ddecs54261.2022.9770137\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a general purpose logic element with eight variations, built using multigate ambipolar transistors, sufficiently capable to replace LUTs in FPGAs. We simulate the new logic element using a 10nm silicon-nanowire three-input-gate transistor model, and compare the proposed element to lookup tables and reconfigurable logic elements from the literature implemented using the same technology model. We compare the different elements for delay, power, and number of transistors, specifically accounting for the cost of configuration storage. Compared to an equivalent LUT, the logic element variation with the most available boolean functions uses 90% of the transistors, with a penalty in delay of 102%, and improved dynamic and static power of 97% and 91%, respectively. The smallest variation uses 42% of the transistors, with improved delay of 76%, and improved dynamic and static power of 43% and 43%, respectively.\",\"PeriodicalId\":334461,\"journal\":{\"name\":\"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ddecs54261.2022.9770137\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ddecs54261.2022.9770137","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Programmable logic elements using multigate ambipolar transistors
We propose a general purpose logic element with eight variations, built using multigate ambipolar transistors, sufficiently capable to replace LUTs in FPGAs. We simulate the new logic element using a 10nm silicon-nanowire three-input-gate transistor model, and compare the proposed element to lookup tables and reconfigurable logic elements from the literature implemented using the same technology model. We compare the different elements for delay, power, and number of transistors, specifically accounting for the cost of configuration storage. Compared to an equivalent LUT, the logic element variation with the most available boolean functions uses 90% of the transistors, with a penalty in delay of 102%, and improved dynamic and static power of 97% and 91%, respectively. The smallest variation uses 42% of the transistors, with improved delay of 76%, and improved dynamic and static power of 43% and 43%, respectively.