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Proceedings Sixth Asian Test Symposium (ATS'97)最新文献

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An effective fault simulation method for core based LSI 一种有效的基于磁芯的LSI故障仿真方法
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643945
T. Yoshida, Reisuke Shimoda, T. Mizokawa, K. Hirayama
{"title":"An effective fault simulation method for core based LSI","authors":"T. Yoshida, Reisuke Shimoda, T. Mizokawa, K. Hirayama","doi":"10.1109/ATS.1997.643945","DOIUrl":"https://doi.org/10.1109/ATS.1997.643945","url":null,"abstract":"We examined effective usage of fault simulation to reduce enormous handling time for fault simulation, and applied it in our LSI development. Random sampling method, DFS (Distributed Fault Simulation), a selection of most suitable FPP(faults per pass) and elimination of hyper faults are applied here to realize necessary handling speed of dozens of times faster than the present usage. It is effective in a fault simulation to simulate the best vector first that increases the fault coverage most. Furthermore, we would like to give a new suggestion that the density of mask patterns is taken into consideration as a factor of fault coverage and also its physical correctness is estimated.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122461444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A XOR-tree based technique for constant testability of configurable FPGAs 基于xor树的可配置fpga恒定可测性技术
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643966
Wei-Kang Huang, M. Zhang, F. Meyer, F. Lombardi
{"title":"A XOR-tree based technique for constant testability of configurable FPGAs","authors":"Wei-Kang Huang, M. Zhang, F. Meyer, F. Lombardi","doi":"10.1109/ATS.1997.643966","DOIUrl":"https://doi.org/10.1109/ATS.1997.643966","url":null,"abstract":"This paper presents a novel approach for testing and diagnosing configurable field programmable gate arrays (FPGAs). The proposed approach is row-based and uses a two-session procedure. The approach arranges some logic blocks to be programmed as XOR-tree (or chain, or cascade) in the first session. The XOR-tree is effectively used as test vehicle for observability. The roles of the CLBs are inverted in the second session. It is shown that the proposed testing arrangement requires a number of tests independent of the number of CLBs in the FPGA (i.e. C-testability is accomplished). Routing is kept local, and compatibility for a CAD implementation is also accomplished.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"C-22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126784016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
An extended march test algorithm for embedded memories 嵌入式存储器的扩展行军测试算法
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643990
Gang-Min Park, Hoon Chang
{"title":"An extended march test algorithm for embedded memories","authors":"Gang-Min Park, Hoon Chang","doi":"10.1109/ATS.1997.643990","DOIUrl":"https://doi.org/10.1109/ATS.1997.643990","url":null,"abstract":"In this paper, an efficient test algorithm and BIST architecture for embedded memories are presented. The proposed test algorithm can fully detect stuck-at fault, transition fault, coupling fault. Moreover, the proposed test algorithm can detect neighborhood pattern sensitive fault, which could not be detected in previous march test algorithms. The proposed test algorithm performs testing for neighborhood pattern sensitive fault using background data, which has been used for word-oriented memory testing.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125188601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Test length for random testing of sequential machines application to RAMs 适用于ram的顺序机器随机测试的测试长度
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643988
R. David
{"title":"Test length for random testing of sequential machines application to RAMs","authors":"R. David","doi":"10.1109/ATS.1997.643988","DOIUrl":"https://doi.org/10.1109/ATS.1997.643988","url":null,"abstract":"For a combinational fault, the probability of nondetection decreases exponentially with the test length L: /spl epsiv/=(1-p/sub f/)/sup L/, where p/sub f/ is the probability of detecting the fault f by a random test vector. For a sequential fault, the problem is more complex because of the memory effect (the probability of detection at time l depends on the vectors previously applied) and the exact solution requires the analysis of a Markov chain modeling the detection process. This paper shows that there is a value, obtained from the transition matrix of the Markov chain, which can take the place of p/sub f/ when the test length is relatively long (this value is different from the average detection probability). From this result and taking into account a particular property of bounded faults in RAMs, several results concerning these faults, already observed by several authors, are shown.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On decomposition of Kleene TDDs Kleene tdd的分解研究
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643964
Y. Iguchi, Tsutomu Sasao, M. Matsuura
{"title":"On decomposition of Kleene TDDs","authors":"Y. Iguchi, Tsutomu Sasao, M. Matsuura","doi":"10.1109/ATS.1997.643964","DOIUrl":"https://doi.org/10.1109/ATS.1997.643964","url":null,"abstract":"Kleene-TDDs are useful for evaluating logic functions in the presence of unknown inputs, 0 or 1. Although Kleene-TDD-based logic simulation is promising, the size of Kleene-TDD for an n-variable function is O(3/sup n//n). Thus, when n is large, the Kleene-TDDs are often too large to build. In this paper, we propose several methods to decompose Kleene-TDDs. By using this method, we can generate smaller Kleene-TDDs for sub-functions independently to reduce the necessary memory. Preliminary experimental results show that the effectiveness of the presented approach.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114652488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Estimating the number of faults using simulator based on generalized stochastic Petri-net model 基于广义随机Petri-net模型的故障模拟器估计方法
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643969
O. Mizuno, S. Kusumoto, T. Kikuno, Yasunari Takagi, Keishi Sakamoto
{"title":"Estimating the number of faults using simulator based on generalized stochastic Petri-net model","authors":"O. Mizuno, S. Kusumoto, T. Kikuno, Yasunari Takagi, Keishi Sakamoto","doi":"10.1109/ATS.1997.643969","DOIUrl":"https://doi.org/10.1109/ATS.1997.643969","url":null,"abstract":"In order to manage software projects quantitatively, we have presented a new model far software project based on generalized stochastic Petri-net model which can take influence of human factors into account, and we have already developed software project simulator based on GSPN model. This paper proposes methods for calculating model parameters in the new model and estimating the number of faults in the design and debug phases of software process. Then we present experimental evaluation of proposed method using a data of actual software development project on a certain company. As the result of case study, we confirmed its effectiveness with respect to estimating the number of faults in the software process.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127680867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Code-disjoint circuits for parity codes 奇偶码的码分离电路
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643929
H. Hartje, M. Gössel, E. Sogomonyan
{"title":"Code-disjoint circuits for parity codes","authors":"H. Hartje, M. Gössel, E. Sogomonyan","doi":"10.1109/ATS.1997.643929","DOIUrl":"https://doi.org/10.1109/ATS.1997.643929","url":null,"abstract":"In this paper it is shown how a circuit, given as a netlist of gates, can be transformed into two different types of code-disjoint circuits. A new method for a joint design of the functional circuit, the output parity and the input parity is proposed. Carefully selected internal nodes of the functional circuit are utilized to reduce the necessary area overhead for the design of input and output parities.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134493325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Embedded test and measurement critical for deep submicron technology 嵌入式测试和测量对深亚微米技术至关重要
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.10004
V. Agarwal
{"title":"Embedded test and measurement critical for deep submicron technology","authors":"V. Agarwal","doi":"10.1109/ATS.1997.10004","DOIUrl":"https://doi.org/10.1109/ATS.1997.10004","url":null,"abstract":"The embedded test and measurement (ETM) technology has been known in the past by its various other names such as Built-In Test Equipment (BITE), Built-In Test (BIT), Built-In Self-Test (BIST), and Self-Test. However, with deep submicron technology, the comprehensive nature and completeness with which the ETM technology can be implemented goes far beyond the scope that its predecessor had planned considered. It is becoming clear that the ETM technology will be a \"must have\" technology that will be required to enable the continued growth of the electronics industry. Some of the key factors responsible for driving the shift to ETM and away from external test and measurement are: at-speed testing, the emerging silicon-on-a-chip methodology, time-to-market, the wide use of embedded memories, better defect coverage for higher quality parts and cost. Also critical are issues such as vertical disintegration of the electronics industry, increased consumerism of electronic products, and increased dependence on reliability of telecommunication, control and computers in the our daily lives. Basic research in the ETM technology in the last twenty years has created solutions that are robust and cost effective.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133577678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A partial scan design method based on n-fold line-up structures 基于n倍排列结构的局部扫描设计方法
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643975
Toshinori Hosokawa, Toshihiro Hiraoka, M. Ohta, M. Muraoka, S. Kuninobu
{"title":"A partial scan design method based on n-fold line-up structures","authors":"Toshinori Hosokawa, Toshihiro Hiraoka, M. Ohta, M. Muraoka, S. Kuninobu","doi":"10.1109/ATS.1997.643975","DOIUrl":"https://doi.org/10.1109/ATS.1997.643975","url":null,"abstract":"We will present a partial scan design method based on n-fold line-up structures and a partial scan design method based on the state justification of pure FFs of load/hold type in order to achieve high fault efficiency for practical LSIs. We will also present a dynamic test sequence compaction method for acyclic structures. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency and reduce the number of test patterns by half.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132534776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Sequential test generation based on circuit pseudo-transformation 基于电路伪变换的顺序测试生成
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643919
S. Ohtake, Tomoo Inoue, H. Fujiwara
{"title":"Sequential test generation based on circuit pseudo-transformation","authors":"S. Ohtake, Tomoo Inoue, H. Fujiwara","doi":"10.1109/ATS.1997.643919","DOIUrl":"https://doi.org/10.1109/ATS.1997.643919","url":null,"abstract":"The test generation problem for a sequential circuit capable of generating tests with combinational test generation complexity can be reduced to that for the combinational circuit formed by replacing each FF in the sequential circuit by a wire. In this paper, we consider an application of this approach to general sequential circuits. We propose a test generation method using circuit pseudo-transformation technique: given a sequential circuit, we extract a subcircuit with balanced structure which is capable of generating tests with combinational test generation complexity, replace each FF in the subcircuit by wire, generate test sequences for the transformed sequential circuit, and finally obtain test sequences for the original sequential circuit. We also estimate the effectiveness of the proposed method by experiment with ISCAS'89 benchmark circuits.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127954836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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