A partial scan design method based on n-fold line-up structures

Abstract

We will present a partial scan design method based on n-fold line-up structures and a partial scan design method based on the state justification of pure FFs of load/hold type in order to achieve high fault efficiency for practical LSIs. We will also present a dynamic test sequence compaction method for acyclic structures. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency and reduce the number of test patterns by half.