{"title":"奇偶码的码分离电路","authors":"H. Hartje, M. Gössel, E. Sogomonyan","doi":"10.1109/ATS.1997.643929","DOIUrl":null,"url":null,"abstract":"In this paper it is shown how a circuit, given as a netlist of gates, can be transformed into two different types of code-disjoint circuits. A new method for a joint design of the functional circuit, the output parity and the input parity is proposed. Carefully selected internal nodes of the functional circuit are utilized to reduce the necessary area overhead for the design of input and output parities.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Code-disjoint circuits for parity codes\",\"authors\":\"H. Hartje, M. Gössel, E. Sogomonyan\",\"doi\":\"10.1109/ATS.1997.643929\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper it is shown how a circuit, given as a netlist of gates, can be transformed into two different types of code-disjoint circuits. A new method for a joint design of the functional circuit, the output parity and the input parity is proposed. Carefully selected internal nodes of the functional circuit are utilized to reduce the necessary area overhead for the design of input and output parities.\",\"PeriodicalId\":330767,\"journal\":{\"name\":\"Proceedings Sixth Asian Test Symposium (ATS'97)\",\"volume\":\"115 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Sixth Asian Test Symposium (ATS'97)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1997.643929\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Sixth Asian Test Symposium (ATS'97)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1997.643929","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper it is shown how a circuit, given as a netlist of gates, can be transformed into two different types of code-disjoint circuits. A new method for a joint design of the functional circuit, the output parity and the input parity is proposed. Carefully selected internal nodes of the functional circuit are utilized to reduce the necessary area overhead for the design of input and output parities.