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Proceedings Sixth Asian Test Symposium (ATS'97)最新文献

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Analog signal metrology for mixed signal ICs 混合信号集成电路的模拟信号计量
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643958
C. Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen
{"title":"Analog signal metrology for mixed signal ICs","authors":"C. Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen","doi":"10.1109/ATS.1997.643958","DOIUrl":"https://doi.org/10.1109/ATS.1997.643958","url":null,"abstract":"Signal reconstruction reconstructs a multiple period low-rate sampled waveform into a one-period high-rate sampled waveform. With which, we are able to provide sufficient samples of analog signals for DSP based testing using on-chip ADCs. Test results show that a 128-sample-per-period waveform can be reconstructed from a 2.4 samples per period waveform sampled by a 20 MHz 8-bit ADC.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122019316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new auto-focus method in critical dimension measurement SEM 关键尺寸测量中一种新的自动对焦方法
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643959
F. Komatsu, H. Motoki, M. Miyoshi
{"title":"A new auto-focus method in critical dimension measurement SEM","authors":"F. Komatsu, H. Motoki, M. Miyoshi","doi":"10.1109/ATS.1997.643959","DOIUrl":"https://doi.org/10.1109/ATS.1997.643959","url":null,"abstract":"We have developed a new auto-focus method using the image processing technology. This method consists of two steps. The first step is the preset of the objective lens condition with the feedback of Z-sensor. In the second step, the pattern recognition of a target hole pattern is performed prior to auto-focusing scan in order to scan E-beam accurately over the pattern. The measurement repeatability (3/spl sigma/) can be achieved within 3.9 nm. The pass rate of 98.7% can be realized in the present auto-focus method.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130930408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and implementation of strongly code disjoint CMOS built-in intermediate voltage sensor for totally self-checking circuits 用于全自检电路的强码分离CMOS内置中压传感器的设计与实现
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643925
Joseph C. W. Pang, M. Wong, Yim-Shu Lee
{"title":"Design and implementation of strongly code disjoint CMOS built-in intermediate voltage sensor for totally self-checking circuits","authors":"Joseph C. W. Pang, M. Wong, Yim-Shu Lee","doi":"10.1109/ATS.1997.643925","DOIUrl":"https://doi.org/10.1109/ATS.1997.643925","url":null,"abstract":"This paper presents a new approach to implement a strongly code-disjoint CMOS built-in intermediate voltage sensor(BIVS). The function of the BIVS is used to detect any intermediate voltage caused by bridging and transistor stuck-on faults in the circuit. Detailed analyses of the proposed circuit have shown that the overall design not only can detect fault in the circuit under test, but also can detect or tolerate the fault in itself. An application example employing the BIVS as the output detection element to enhance the effectiveness of the totally selfchecking circuit is given.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132264001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Random pattern testable design with partial circuit duplication 部分电路重复随机模式测试设计
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643982
H. Yokoyama, X. Wen, H. Tamamoto
{"title":"Random pattern testable design with partial circuit duplication","authors":"H. Yokoyama, X. Wen, H. Tamamoto","doi":"10.1109/ATS.1997.643982","DOIUrl":"https://doi.org/10.1109/ATS.1997.643982","url":null,"abstract":"The advantage of random testing is that test application can be performed at a low cost in the BIST scheme. However, not all circuits are random pattern testable. In this paper, we present a method for improving random pattern testability of logic circuits by partial circuit duplication. The basic idea is to detect random pattern resistant faults by using the difference between the duplicated part of a circuit and the original part. Experimental results on benchmark circuits show that high fault coverage can be achieved with a very small amount of hardware overhead.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114192692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the capability of delay tests to detect bridges and opens 延迟试验检测桥梁和开口的能力
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643976
S. Chakravarty
{"title":"On the capability of delay tests to detect bridges and opens","authors":"S. Chakravarty","doi":"10.1109/ATS.1997.643976","DOIUrl":"https://doi.org/10.1109/ATS.1997.643976","url":null,"abstract":"Recent empirical and simulation studies show that adding at-speed testing to the test suite helps in detecting defective ICs missed by slow-speed and I/sub DDQ/ testing. At-speed testing attempts to detect ICs with defects, like bridges and opens, which cause faulty dynamic logic behavior. Path delay tests and transition tests are two popular tests used during at-speed testing. We show that these tests often fail to detect many bridges and opens which cause faulty dynamic behavior. Computing at speed tests is therefore fundamentally different from computing delay tests for parametric testing and new techniques need to be developed.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114924511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Testing for the programming circuit of LUT-based FPGAs 基于lut的fpga编程电路的测试
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643965
H. Michinishi, T. Yokohira, T. Okamoto, Tomoo Inoue, H. Fujiwara
{"title":"Testing for the programming circuit of LUT-based FPGAs","authors":"H. Michinishi, T. Yokohira, T. Okamoto, Tomoo Inoue, H. Fujiwara","doi":"10.1109/ATS.1997.643965","DOIUrl":"https://doi.org/10.1109/ATS.1997.643965","url":null,"abstract":"The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121892822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Power supply current monitoring techniques for testing PLLs 用于测试锁相环的电源电流监测技术
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643984
Maneesha Dalmia, A. Ivanov, S. Tabatabaei
{"title":"Power supply current monitoring techniques for testing PLLs","authors":"Maneesha Dalmia, A. Ivanov, S. Tabatabaei","doi":"10.1109/ATS.1997.643984","DOIUrl":"https://doi.org/10.1109/ATS.1997.643984","url":null,"abstract":"The effectiveness of current testing for digital IC's has led researchers to explore the possibility of extending this concept to testing analog blocks of mixed-signal ICs. Unfortunately, test techniques developed for commonly-studied analog blocks such as op-amps and filters do not apply to non-linear blocks such as phase-locked loops. This paper focuses on investigating the effectiveness of using an operating power supply current monitoring technique to detect potential faults in a phase-locked loop (PLL) circuit.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125219967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Guaranteeing testability in re-encoding for low power 保证低功耗重编码的可测试性
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643912
S. Chiusano, Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda
{"title":"Guaranteeing testability in re-encoding for low power","authors":"S. Chiusano, Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda","doi":"10.1109/ATS.1997.643912","DOIUrl":"https://doi.org/10.1109/ATS.1997.643912","url":null,"abstract":"This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimization algorithm is proposed, which is able to explore the trade-off between them. The algorithm is based on a newly proposed power estimation function, and on an estimate of the expected rest length of a pseudo-random rest session. Given these estimates a Genetic Algorithm, exploiting some symbolic computations with BDDs, provides a state reencoding for the circuit. The algorithm is experimental shown both to provide good results from the power optimization point of view, and to be able to sacrifice, on the designer's request, some of the power and area optimization in favor of testability improvement.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124570553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Supply current test for unit-to-unit variations of electrical characteristics in gates 栅极中单元间电特性变化的供电电流试验
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643985
M. Hashizume, T. Kuchii, T. Tamesada
{"title":"Supply current test for unit-to-unit variations of electrical characteristics in gates","authors":"M. Hashizume, T. Kuchii, T. Tamesada","doi":"10.1109/ATS.1997.643985","DOIUrl":"https://doi.org/10.1109/ATS.1997.643985","url":null,"abstract":"A practical supply current test method is proposed and the experimental evaluation results are presented. In the method, the unit-to-unit variation of electrical characteristics in each logic gate is modeled as a Gaussian distribution and faults are detected with a statistical hypothesis technique.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114175462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An algorithm for all-du-path testing coverage of shared memory parallel programs 共享内存并行程序的全双路径测试覆盖率算法
Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI: 10.1109/ATS.1997.643968
Cheer-Sun D. Yang, L. Pollock
{"title":"An algorithm for all-du-path testing coverage of shared memory parallel programs","authors":"Cheer-Sun D. Yang, L. Pollock","doi":"10.1109/ATS.1997.643968","DOIUrl":"https://doi.org/10.1109/ATS.1997.643968","url":null,"abstract":"Little attention has focused on applying traditional testing methodology to parallel programs. This paper discusses issues involved in providing all-du-path coverage in shared memory parallel programs, and describes an algorithm for finding a set of paths covering all define-use pairs. To our knowledge, this is the first effort of this kind.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116265661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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