{"title":"On the compaction of test sets produced by genetic optimization","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.1997.643906","DOIUrl":"https://doi.org/10.1109/ATS.1997.643906","url":null,"abstract":"A previously proposed test generation procedure based on genetic optimization proved to have several advantages in terms of fault coverage; however, it produced large test set sizes. We investigate a way to generate compact test sets using this procedure by embedding it into a test compaction procedure. The compaction procedure constructs a compact test set out of the best tests contained in several test sets produced by the genetic optimization based test generation procedure. Using this approach, it is possible to significantly reduce the test set sizes obtained.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124535822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Built-in current sensor designs based on the bulk-driven technique","authors":"Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee","doi":"10.1109/ATS.1997.643987","DOIUrl":"https://doi.org/10.1109/ATS.1997.643987","url":null,"abstract":"Recently the bulk-driven current mirror technique has been employed in built-in current sensors for low voltage environment. This paper proposes 4 arrangements of built-in current sensors based on this technique. They are mainly different in biasing schemes end respectively take the advantages of simplicity, accuracy, flexibility and low power dissipation. From experiments, these sensors have small performance impact which causes only 0.3 V of power supply voltage drop and 0.3 ns delay of circuit speed degradation. These sensors require single external power supply and small area overhead.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128021081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Computing stress tests for interconnect defects","authors":"V. Dabholkar, S. Chakravarty","doi":"10.1109/ATS.1997.643950","DOIUrl":"https://doi.org/10.1109/ATS.1997.643950","url":null,"abstract":"Reliability screens are used to reduce infant mortality. The quality of the stress test set used during. The screening process has a direct bearing on the effectiveness of the screen. We have formally studied the problem of computing good quality stress tests for some commonly occurring defects like gate-oxide shorts and interconnect defects. Methods to compute stress tests for gate-oxide defects have been discussed elsewhere. Here we present a formal study of the problem of computing stress rests for interconnect defects.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115271128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On acceleration of logic circuits optimization using implication relations","authors":"H. Ichihara, K. Kinoshita","doi":"10.1109/ATS.1997.643962","DOIUrl":"https://doi.org/10.1109/ATS.1997.643962","url":null,"abstract":"In logic synthesis the multi-level logic optimization methods using implication analysis has high performance but it needs a lot of computational time because of using test pattern generation to identify redundant faults. In this paper we proposed a fast redundancy identification method using implication relation instead of test pattern generation. Experimental results for benchmark circuits clearly show that the proposed method can accelerate the speed to identify redundancies without declining of the ability of the optimization.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128319254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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