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2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)最新文献

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Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis 层次量子电路合成中减少量子比特的可逆卵石游戏
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-21 DOI: 10.1109/ISMVL.2019.00026
Debjyoti Bhattacharjee, Mathias Soeken, Srijit Dutta, A. Chattopadhyay, G. Micheli
{"title":"Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis","authors":"Debjyoti Bhattacharjee, Mathias Soeken, Srijit Dutta, A. Chattopadhyay, G. Micheli","doi":"10.1109/ISMVL.2019.00026","DOIUrl":"https://doi.org/10.1109/ISMVL.2019.00026","url":null,"abstract":"Hierarchical reversible logic synthesis can find quantum circuits for large combinational functions. The price for a better scalability compared to functional synthesis approaches is the requirement for many additional qubits to store temporary results of the hierarchical input representation. However, implementing a quantum circuit with large number of qubits is a major hurdle. In this paper, we demonstrate and establish how reversible pebble games can be used to reduce the number of stored temporary results, thereby reducing the qubit count. Our proposed algorithm can be constrained with number of qubits, which is aimed to meet. Experimental studies show that the qubit count can be significantly reduced (by up to 63.2%) compared to the state-of-the-art algorithms, at the cost of additional gate count.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121284028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Task Value Calculus: Multi-Objective Trade off Analysis Using Multiple-Valued Decision Diagrams 任务价值演算:使用多值决策图的多目标权衡分析
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-21 DOI: 10.1109/ISMVL.2019.00030
Tyler Giallanza, Erik Gabrielsen, Michael A. Taylor, Eric C. Larson, M. Thornton
{"title":"Task Value Calculus: Multi-Objective Trade off Analysis Using Multiple-Valued Decision Diagrams","authors":"Tyler Giallanza, Erik Gabrielsen, Michael A. Taylor, Eric C. Larson, M. Thornton","doi":"10.1109/ISMVL.2019.00030","DOIUrl":"https://doi.org/10.1109/ISMVL.2019.00030","url":null,"abstract":"Most multiple-objective optimization algorithms utilize continuous input variables. Given that many decision variables in common use-cases are discrete rather than continuous, we develop a multiple-objective optimization framework over discrete variables known as task value calculus (TVC). The underlying mathematical models in TVC utilize a multiple-valued algebraic framework where both the objective functions and the system or process structure models are represented as multiple-valued functions. TVC allows for fast multiple-objective optimization through the use of the multiple-valued decision diagram (MDD) data structure. The algorithms and structures internal to TVC are described and experimental results are provided. TVC is implemented with a simple graphical user interface making it suitable for use by both laypersons and domain experts.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122177295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Machine Learning Algorithm to Reduce Prediction Error and Accelerate Learning Curve for Very Large Datasets 一种新的机器学习算法来减少预测误差并加速超大数据集的学习曲线
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-21 DOI: 10.1109/ISMVL.2019.00025
Wenjun Hou, M. Perkowski
{"title":"A Novel Machine Learning Algorithm to Reduce Prediction Error and Accelerate Learning Curve for Very Large Datasets","authors":"Wenjun Hou, M. Perkowski","doi":"10.1109/ISMVL.2019.00025","DOIUrl":"https://doi.org/10.1109/ISMVL.2019.00025","url":null,"abstract":"This paper presents a novel machine learning algorithm with an improved accuracy and a faster learning curve, for very large datasets. Previously, an algorithm using lr-partitions was designed to improve upon C4.5. However, this algorithm has a relatively high percentage of undefined combinations of attribute values in its final results, increasing the learning error. In this paper, a new type of clustering algorithm was proposed to generate output values for those undefined combinations, thus accelerating the learning curve and reducing the prediction error by several percentage points on various popular datasets from the UCI Machine Learning Database.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130274638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks 基于mtj补偿器的二值化神经网络电流模式线性和计数电路设计
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-21 DOI: 10.1109/ISMVL.2019.00024
Tomoki Chiba, M. Natsui, T. Hanyu
{"title":"Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks","authors":"Tomoki Chiba, M. Natsui, T. Hanyu","doi":"10.1109/ISMVL.2019.00024","DOIUrl":"https://doi.org/10.1109/ISMVL.2019.00024","url":null,"abstract":"A bitcounting operation, which counts l's/0's in input values and decides the output depending on their majority, is one of the important operations in binarized neural networks (BNNs). In this paper, we propose a bitcounting circuit for compact and low-power BNN hardware. This circuit performs the bitcounting operation by utilizing current-mode linear summation, which achieves a high-speed and low-power operation as well as a compact circuit. In order to guarantee a reliable analog operation of the circuit under possible process variation conditions, magnetic tunnel junction (MTJ) devices integrated with the bitcounting circuit can adjust its operating point and keep this adjustment information in a nonvolatile manner. Through an experimental-data-based evaluation of a 25-input bitcounting circuit under a 40-nm MOS/MTJ-hybrid process, we show that this circuit reduces the power-delay product and circuit area by 92% and 93%, respectively, compared to a conventional accumulation-tree-based one, while guaranteeing the correct operation under the process variation condition assumed on the target fabrication process technology.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"270 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134472789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The Invariance of Spectral-Kolmogorov-Type Statistics for Estimating Genomic Similarity 估计基因组相似性的光谱kolmogorov型统计量的不变性
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ISMVL.2019.00021
Micah Thornton
{"title":"The Invariance of Spectral-Kolmogorov-Type Statistics for Estimating Genomic Similarity","authors":"Micah Thornton","doi":"10.1109/ISMVL.2019.00021","DOIUrl":"https://doi.org/10.1109/ISMVL.2019.00021","url":null,"abstract":"Accurate and efficient comparison of genetic sequences is an important undertaking that has applications in medicine as well as informing the hierarchical clustering of organisms. Genomic comparison is important for full genomic sequences across individuals of the same or different species as in phylogenies and also within organisms as in pedigrees. Given the enormity of the different genomes and their respective sizes, such comparisons are well-known to be computationally intensive and we are motivated to find more efficient and accurate means for the genomic comparison problem. This paper introduces a metric that is computed via the proposed methodology of comparing the empirical distributions of the observed k-mers among one or more genetic sequences. This metric is in fact a Kolmogorov-Smirnoff-like statistic since it is the supremum of differences in the empirical distribution functions. Specifically, genetic sequences are represented as quaternary or radix-4 encoded sequences that allow the metric to be computed and the metric is shown to produce similar clusterings when computed via spectral coefficients. Further, we investigate the use of spectral methods, in particular the Walsh-Hadamard spectrum, of the quaternary-encoded genetic sequence and observe computed maximal spectral densities as a basis of comparison. The invariance of the Kolmogorov-Smirnoff-like statistic when it is computed in the Walsh-Hadamard domain can enable faster comparison computations through the use of spectral properties. For example, the convolution of two sequences becomes a simple multiplication in the spectral domain.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116874535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions 基于动态规划的索引生成函数最优线性分解方法
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ISMVL.2019.00033
Shinobu Nagayama, Tsutomu Sasao, J. T. Butler
{"title":"A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions","authors":"Shinobu Nagayama, Tsutomu Sasao, J. T. Butler","doi":"10.1109/ISMVL.2019.00033","DOIUrl":"https://doi.org/10.1109/ISMVL.2019.00033","url":null,"abstract":"The problem addressed in this paper is minimization of the number of linear functions in a linear decomposition. This paper proposes an exact minimization method based on dynamic programming for index generation functions. The proposed method searches for an optimum solution while recursively dividing an index set of a given index generation function. To use partial solutions efficiently in solution search, the proposed method represents partitions of an index set compactly and uniquely by zero-suppressed binary decision diagrams (ZDDs). Existing methods based on a branch-and-bound approach search for a solution sequentially in a depth-first manner. On the other hand, the proposed method searches for multiple partial solutions in parallel in a breadth-first manner. Thus, once a solution is found, we can terminate the search process. This is because the depth of searches corresponds to the number of linear functions. Experimental results using benchmark index generation functions show the effectiveness of the proposed method.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129005591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Quasi-Postan Logic Hazard of Postan Signals 邮政信号的拟邮政逻辑危害
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ISMVL.2019.00034
Maciej Rudziecki
{"title":"Quasi-Postan Logic Hazard of Postan Signals","authors":"Maciej Rudziecki","doi":"10.1109/ISMVL.2019.00034","DOIUrl":"https://doi.org/10.1109/ISMVL.2019.00034","url":null,"abstract":"Every quasi-Postan function is a coproduct of a chain and quasi-Boolean functions. The quasi-Postan logic hazard of Postan signals are described by means of quasi-Boolean logic hazard of Boolean signals. The proof that elimination of the quasi-Postan logic hazard is achievable by eliminating the quasi-Boolean logic hazard form Boolean signals is provided in the paper.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134544224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The mathematics of Ivo Rosenberg 伊沃·罗森博格的数学
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ISMVL.2019.00016
Miguel Couceiro, L. Haddad, M. Pouzet
{"title":"The mathematics of Ivo Rosenberg","authors":"Miguel Couceiro, L. Haddad, M. Pouzet","doi":"10.1109/ISMVL.2019.00016","DOIUrl":"https://doi.org/10.1109/ISMVL.2019.00016","url":null,"abstract":"We survey some of the most well known results of Professor Ivo G. Rosenberg as well as present some new ones related to the study of maximal partial clones and their intersections.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"3177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127475886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures IBM体系结构中Clifford+T电路的CNOT门映射
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ISMVL.2019.00010
Alexandre A. A. de Almeida, G. Dueck, A. C. R. D. Silva
{"title":"CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures","authors":"Alexandre A. A. de Almeida, G. Dueck, A. C. R. D. Silva","doi":"10.1109/ISMVL.2019.00010","DOIUrl":"https://doi.org/10.1109/ISMVL.2019.00010","url":null,"abstract":"IBM architectures impose some restrictions the quantum circuits that can be implemented. Only gates from Clifford+T gate library can be used and not all of the CNOT gates are available. Some of the CNOT need to be mapped into a sequence of gates. In this paper we present a set of mappings to conform to the restrictions imposed by IBM's architectures. These mappings require fewer gates than SWAP gates. It is well known, that permuting the qubits will yield circuits with different number of gates. The design in this paper uses efficient mappings with qubit permutations to obtain circuits with a reduced number of gates. Results have shown that the proposed approach reduces circuits by up to 64% compared with Qiskit and up to 42% compared with another mapping algorithm.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122715972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Publisher's Information 出版商的信息
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ismvl.2019.00045
{"title":"Publisher's Information","authors":"","doi":"10.1109/ismvl.2019.00045","DOIUrl":"https://doi.org/10.1109/ismvl.2019.00045","url":null,"abstract":"","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116722616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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