2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)最新文献_第4页

Fine-Grained Complexity of Constraint Satisfaction Problems through Partial Polymorphisms: A Survey 基于部分多态性的约束满足问题的细粒度复杂性研究综述

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ISMVL.2019.00037

Miguel Couceiro, L. Haddad, Victor Lagerkvist

引用次数: 6

Message from the Program Chair 来自项目主席的信息

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ismvl.2019.00006

H. Suhartanto

{"title":"Message from the Program Chair","authors":"H. Suhartanto","doi":"10.1109/ismvl.2019.00006","DOIUrl":"https://doi.org/10.1109/ismvl.2019.00006","url":null,"abstract":"Welcome to the 9th International Conference on High Performance Computing. The conference features 10 contributed paper sessions with 57 papers, 2 invited sessions with 9 papers, an industrial track session, a poster session, 5 keynote addresses, 10 tutorials, and 5 workshops. The 57 contributed papers are from 12 countries. The 10 contributed paper sessions were put together by a distinguished and international program committee that comprised 56 committee members and 5 program vice-chairs: Oscar Ibarra (Algorithms), Vipin Kumar (Applications), Michel Cosnard (Architecture), Mani Srivastava (Communication Networks), and Francis Lau (Systems Software). Following a rigorous review process, the program committee selected 57 of the 145 papers that were submitted in response to the call for papers for presentation at the conference and inclusion in the conference proceedings. The 2 invited sessions were organized by Vijay Kumar (Biocomputation) and Viktor Prasanna (Embedded Systems), the industrial track by Sudheendra Hangal, the poster session by Paul Roe and Rajkumar Buyya, the keynote addresses by Cauligi Raghavendra, the tutorials by Srinivas Aluru, and the workshops by C.P. Ravikumar. I wish to thank the entire program committee and especially the program vice-chairs for the excellent job they did in the review of the 145 submitted papers and subsequent selection of papers. Thanks also go to those who organized the remaining sessions, mentioned above, that make up the conference as well as to those who performed the administrative functions that are essential to the success of this conference. Finally, I thank Viktor Prasanna for giving me the opportunity to serve as program chair of this conference.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"500 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132235093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

2019 IEEE 49th International Symposium on Multiple-Valued Logic 2019 IEEE第49届多值逻辑国际研讨会

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ismvl.2019.00001

引用次数: 0

Entanglement in Higher-Radix Quantum Systems 高基数量子系统中的纠缠

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ISMVL.2019.00028

Kaitlin N. Smith, M. Thornton

引用次数: 4

One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits 一个额外的量子位就足够了:量子电路中布尔分量的编码嵌入

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ISMVL.2019.00009

Alwin Zulehner, Philipp Niemann, R. Drechsler, R. Wille

{"title":"One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits","authors":"Alwin Zulehner, Philipp Niemann, R. Drechsler, R. Wille","doi":"10.1109/ISMVL.2019.00009","DOIUrl":"https://doi.org/10.1109/ISMVL.2019.00009","url":null,"abstract":"Research on quantum computing has recently gained significant momentum since first physical devices became available. Many quantum algorithms make use of so-called oracles that implement Boolean functions and are queried with highly superposed input states in order to evaluate the implemented Boolean function for many different input patterns in parallel. To simplify or enable a realization of these oracles in quantum logic in the first place, the Boolean reversible functions to be realized usually need to be broken down into several non-reversible sub-functions. However, since quantum logic is inherently reversible, these sub-functions have to be realized in a reversible fashion by adding further qubits in order to make the output patterns distinguishable (a process that is also known as embedding). This usually results in a significant increase of the qubits required in total. In this work, we show how this overhead can be significantly reduced by utilizing coding. More precisely, we prove that one additional qubit is always enough to embed any non-reversible function into a reversible one by using a variable-length encoding of the output patterns. Moreover, we characterize those functions that do not require an additional qubit at all. The made observations show that coding often allows one to undercut the usually considered minimum of additional qubits in sub-functions of oracles by far.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128137925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Synthesis of Nondeterministic Behavior in Recombinase-Based Genetic Circuits 基于重组酶的遗传回路中不确定性行为的综合

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ISMVL.2019.00042

Zi-Jun Lin, Wei-Chih Huang, J. H. Jiang

引用次数: 0

The Inclusion Structure of Boolean Weak Bases 布尔弱碱的包含结构

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ISMVL.2019.00014

Victor Lagerkvist, Biman Roy

引用次数: 1

Noise Convolutional Neural Networks and FPGA Implementation 噪声卷积神经网络及其FPGA实现

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2019-05-01 DOI: 10.1109/ISMVL.2019.00023

Atsuki Munakata, Hiroki Nakahara, Shimpei Sato

{"title":"Noise Convolutional Neural Networks and FPGA Implementation","authors":"Atsuki Munakata, Hiroki Nakahara, Shimpei Sato","doi":"10.1109/ISMVL.2019.00023","DOIUrl":"https://doi.org/10.1109/ISMVL.2019.00023","url":null,"abstract":"Convolutional neural networks (CNNs) are primarily a cascaded set of pattern recognition filters, which are trained by big data. It enables us to solve complex problems of computer vision applications. A conventional CNN requires numerous parameters (weights) and computations. In this study, we propose a noise CNN (NCNN), which consists of conventional convolutional operation in the former layer and a noise convolutional operation in the latter layers. Noise convolution can be realized by pointwise convolution with the addition of noise to retain recognition accuracy for a large kernel size convolution layer. Using data obtained from theoretical analysis, we apply various convolution layers including a conventional convolution in the former layer and a point-wise convolution with noise in the latter one. Further, we propose an architecture for a noise convolution operation with a pseudo-random circuit as the noise generator. We implement the proposed NCNN in the Xilinx Inc. ZCU104 FPGA evaluation board. The experimental results show that the proposed NCNN can preserve recognition accuracy and achieve high performance.","PeriodicalId":329986,"journal":{"name":"2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"38 31","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113993720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), Fredericton, NB, Canada, May 21-23, 2019 2019 IEEE第49届多值逻辑国际研讨会，加拿大，弗雷德里克顿，2019年5月21-23日

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 1900-01-01 DOI: 10.1109/ismvl.2019.00002

引用次数: 0