基于mtj补偿器的二值化神经网络电流模式线性和计数电路设计

Tomoki Chiba, M. Natsui, T. Hanyu
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引用次数: 2

摘要

位计数运算是二值化神经网络(bnn)中的重要运算之一,它对输入值中的1 /0进行计数,并根据它们的多数决定输出。在本文中,我们提出了一种用于紧凑和低功耗BNN硬件的位计数电路。该电路通过利用电流模式线性求和来执行位计数操作,从而实现高速低功耗操作以及紧凑的电路。为了保证电路在可能的工艺变化条件下的可靠模拟运行,与计数电路集成的磁隧道结(MTJ)器件可以调整其工作点,并以非易失性的方式保持该调整信息。通过对40 nm MOS/ mtj混合工艺下的25输入计数电路的实验数据评估,我们表明,与传统的基于累积树的电路相比,该电路的功率延迟积和电路面积分别减少了92%和93%,同时保证了在目标制造工艺技术假设的工艺变化条件下的正确运行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks
A bitcounting operation, which counts l's/0's in input values and decides the output depending on their majority, is one of the important operations in binarized neural networks (BNNs). In this paper, we propose a bitcounting circuit for compact and low-power BNN hardware. This circuit performs the bitcounting operation by utilizing current-mode linear summation, which achieves a high-speed and low-power operation as well as a compact circuit. In order to guarantee a reliable analog operation of the circuit under possible process variation conditions, magnetic tunnel junction (MTJ) devices integrated with the bitcounting circuit can adjust its operating point and keep this adjustment information in a nonvolatile manner. Through an experimental-data-based evaluation of a 25-input bitcounting circuit under a 40-nm MOS/MTJ-hybrid process, we show that this circuit reduces the power-delay product and circuit area by 92% and 93%, respectively, compared to a conventional accumulation-tree-based one, while guaranteeing the correct operation under the process variation condition assumed on the target fabrication process technology.
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