2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition最新文献

{"title":"Optimized adaptive layout technique for hybrid systems in foil","authors":"G. Alavi, H. Sailer, B. Albrecht, C. Harendt, J. Burghartz","doi":"10.23919/EMPC.2017.8346851","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346851","url":null,"abstract":"Compactness, cost, flexibility, and size of electronic devices play an important role for next generation consumer electronics. Flexible hybrid system in foil (HySiF) technology provides an optimum solution by combining low-cost, large and flexible organic with high circuit performance silicon [1]. In this paper, the recently published process flow of integrating micro-hybrid system in polymer foil, the so called Chip-Film Patch (CFP) based on adaptive layout, is analyzed and optimized towards increasing overlay accuracy [2]. In this matter, the overlay accuracy of adaptive layout for a wafer level embedding of chips with different thicknesses has successfully achieved measured below 1 μm in x-axis and y-axis for any arbitrary position on the embedded chip. To the best of our knowledge, this is one of the best ever achieved interconnect accuracy in assembly of thin chips in foil.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127607975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of selective conformal coating process based on advanced packaging for harsh environments","authors":"E. Cadalen, O. Maire, D. Manteigas","doi":"10.23919/EMPC.2017.8346876","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346876","url":null,"abstract":"Conformai coating has been traditionally used to protect Printed Circuit Board Assemblies (PCBA) in harsh environments. The benefit of conformal coating is usually enhanced resistance to mechanical and thermal stresses. Various coating techniques exist, including brushing, dipping and spraying. Today, automation makes selective coating possible. The biggest improvements include: no masking time before coating, chemicals confinement and delivery of a replicable and repeatable process. When using an automated platform, a balance between two major problems must be considered: minimum pattern size and specified thickness range. At the same time, current improvements in selective coating must deal with new schemes: heterogeneous integration and high-density integration. Among drop-on-demand solutions, inkjet is used extensively for printing applications while jetting based on mechanical collision is used in advanced packaging. Based on inkjet knowhow, a theoretical approach has been introduced and then compared with actual experimental results. Both areas are discussed and combined in this paper.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131239281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of the combination of stress buffer layer and wafer level underfill on 3D IC assembly using thermal compression bonding","authors":"F. Duval, T. Wang, P. Bex, C. Gerets, M. Lofrano, K. Rebibis, E. Sleeckx, E. Beyne","doi":"10.23919/EMPC.2017.8346836","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346836","url":null,"abstract":"This study focuses on the investigation of a buffer layer (BL) spin-on dielectric polymer material in combination with a dry-film underfill (WLUF) on the electrical and mechanical performances of 50μm, 40μm and 20μm pitch Sn-based solder μbumps 3D stacked test structures. Thermo-mechanical stresses are generated by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the other materials, including metals, underfill. The objective is to verify whether the use of a medium-stiff polymer, partially replacing the WLUF, can help to reduce the induced stresses in the stack during thermo-compression bonding (TCB) and provide more reliable interconnects. First, stacks with 3μm BL and 15μm WLUF were built by TCB so that Daisy Chains (DC's) at 50μm pitch could be electrically measured exhibiting a high yield of > ∼90%. Next, package reliability testing including Thermal Cycling (TCT) and unbiased Humidity Accelerated Stress (uHAST) were conducted showing no significant changes up to 1000 cycles and 168 hours for TCT and uHAST respectively. Second, the same materials were used in a more aggressive test vehicle (TV) with μbump pitch of 40 and 20μιη. N=4 die stacks could be produced using a collective bonding approach enabling to achieve an electrical yield of about ∼80 to 90% for both 40 and 20μm DC's at all levels of the stack. Finally, a Finite Element Model (FEM) was built to understand the impact of the BL in terms of mechanical stress at the μbump level. It was shown that the BL does not significantly contribute to a reduction in the level of thermo-mechanical stresses. However the Cu plastic deformation is reduced in presence of the BL indicating that the risk of bump failure is lower.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123537716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High speed interfaces for chip to chip communication on interposer based integration","authors":"Muhammad Waqas Chaudhary, A. Heinig","doi":"10.23919/EMPC.2017.8346872","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346872","url":null,"abstract":"Interposer can offer higher number of interconnect and overall larger bandwidth per unit area and watts as compared to PCB based systems. One of the most commonly discussed high speed interfaces are the memory to processor interfaces which run at high clock rates and transfer data without error. There are a number of constraints to designing these memory systems in PCBs especially the correctly matched on die terminations which not only costs silicon area on the memory die but also costs a lot of power. In this work, it will be shown that silicon interposer based interfaces can support the high speed memory interfaces and can meet the electrical specifications of such interfaces while saving a lot of area. DDR3 memory interface is used as the test case to prove this statement.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122846599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Portable reactor with LTCC electrodes for production of plasma activated water","authors":"Jan Macioszczyk, P. Olszewski, L. Golonka, P. Jamróz","doi":"10.23919/EMPC.2017.8346922","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346922","url":null,"abstract":"Atmospheric pressure plasmas, its physic and chemistry attract increasing attention of researchers. In the article portable Plasma Activated Water (PAW) production device is presented. Design and technology of polymer-ceramic, portable device is described in details. It can operate in continuous liquid flow-through mode. Optical characterization of discharge, as well as pH and conductivity measurements of PAW, are described for different gas atmospheres. Results are presented and discussed.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125500001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental investigation on 3D metal interconnection for HySiF(hybrid system in flexible) devices using electrohydrodynamic(EHD) system","authors":"Joon Yub Song, Yongjin Kim, Jae Hak Lee, S. Kim","doi":"10.23919/EMPC.2017.8346835","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346835","url":null,"abstract":"For many years, it has been accepted that the flexible applications can not show high device performance and efficiency due to its inherent material issues while the Si based chips present a totally different aspect (high performance but low flexibility). However, recently, this conventional stereotype is being challenged because the new concept called HySiF (hybrid system in flexible) devices merges two different aspect of the benefits such as high device performance and high mechanical flexibility. In addition, the HySiF devices can also be applied to various applications such as wearable devices, sweat sensors, flexible displays, smart cards, etc which is why this new technical trend starts drawing tremendous attention from many people and research fields. However, while there are diverse technical challenges to commercialize the HySiF devices, we are trying to focus on the fabrication of producing Ag based 3D step-covered metal interconnection using a electrohydrodynamic (EHD) system targeting for the electrical connection between any types of functional Si based chips on a flexible substrate. In order to create 3D step-covered metal interconnection, we control the line width (10∼50 μm) hy optimizing the EHD parameters (flow rate:μl/min, working height: μm, applied voltage: kV, velocity: mm/s, acceleration: mm/s2) that covers various step heights (0 μm ∼ 10 μm) utilizing the Ag nanoparticle based metal ink with a control of the sintering temperature less than 200 °C. As a specific application, 5 μm thick micro-LED chips with a 4×4 array were roll-transferred on the PI substrate and were successfully interconnected using the Ag metal ink sintered at 150 °C maintaining its electrical device performance even under the bending condition (diameter=5mm). As a result, we expect that our work can create lots of opportunities for any kinds of future HySiF applications by eliminating the face-up 3D interconnection issues.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115990017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of dry-patching superhydrophobic flexible platform for HySiF (hybrid system in flexible) applications","authors":"Yongjin Kim, S. Zaidi, Jae Hak Lee, S. Kim, J. Song","doi":"10.23919/EMPC.2017.8346832","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346832","url":null,"abstract":"As the performance of flexible devices including HySiF (hybrid system in flexible) applications has been increased with maintaining its mechanical flexibility, the concept for HySiF is considered as the next generation technology which can possibly open a huge/various/new market. Since HySiF applications can target for various areas such as wearable devices, flexible sensors, flexible display, etc., we think there should be a strong need for the platform of the flexible substrate that can be utilized to any kind of HySiF applications. In order to provide the flexible platform, we focused on the fabrication of a dry-patching superhydrophobic (contact angle >150°) flexible substrate using a solution based polymer casting method by adapting a stamping method for future mass production. While there are two different patching types such as wet-patching and dry-patching, we chose to utilize the dry-patching way because it lasts the patching performance very long without any further or extra treatment (longer than a month). In addition, to create the superhydrophobic characteristic of the substrate, we used a solution based transparent polyimide and fabricated pillar structures (pillar height=30um) which play a crucial role to change the surface condition from Wenzel state to Cassie-Baxter state (contact angle >150°) by creating the air pocket effect between the pillars. With those work, we also achieved a very low hysteresis contact angle (<10°) providing a self-cleaning effect on the surface the can also be a critical factor for a long term use and reliability. With achieving the superhydrophobicity, we also maximized the transparency of the platform substrate by controlling the gap of the pillars (10∼90 um). Finally, we expect that our platform work can help the HySiF target product to commercialize in the near future.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121259623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Sintered Ag joints on copper lead frame TO220 by pressure sintering process with improved reliability and bonding strength","authors":"Ly May Chew, W. Schmitt, Jens Nachreiner, D. Schnee","doi":"10.23919/EMPC.2017.8346904","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346904","url":null,"abstract":"In recent years silver sinter materials have attracted rising attention as interconnect materials in the power electronic devices mainly due to the requirement for devices with longer lifetime, higher efficiency, lower manufacturing cost and the most important is devices that do not contain lead. Silver sintering process are generally classified as pressure and nonpressure sintering process based on the presence or absence of applied pressure during sintering process. Non-pressure sintering process is the common process for lead frame TO220 application. Silver sinter paste is usually dispensed on the lead frame and followed by die placement. Subsequently, non-pressure sintering process is performed in a programmable oven under nitrogen or air atmosphere. Typical non-pressure sintering profile takes approximately 4 hours to complete. The porosity of sinter layer obtained by non-pressure sintering process is higher than the porosity of sinter layer obtained by pressure sintering process. It is known that thermal and electrical conductivities are strongly related to the porosity of sinter layer. Thermal and electrical conductivities increase with increasing density of silver sintered joints. The porosity of sinter layer can be decreased by applying pressure during sintering process. The main focuses of this study are to increase the bonding strength of silver sintered joints on TO220 lead frame and to shorten the total process time.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"39 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126219012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced heat spreading in LTCC packages utilizing thick silver tape in the co-fire process","authors":"T. Welker, N. Gutzeit, Jens Müller","doi":"10.23919/EMPC.2017.8346859","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346859","url":null,"abstract":"The integration density in semiconductor devices has significantly increased in the last years. This trend is already described by Moore's law what forecasts a doubling of the integration density every two years. This evolution makes greater demands on the substrate technology which is used for the first level interconnect between the semiconductor and the device package. Higher pattern resolution is required to connect more functions on a smaller chip. Also the thermal performance of the chip carrying substrate is a crucial issue. The increased integration density leads to a higher power density, thus more heat has to dissipate on a smaller area. Thus, substrates with a high thermal conductivity (e. g. direct bonded copper (DBC)) are utilized. However, the reduced pattern resolution caused by thick metal layers is disadvantageous for this substrate technology. Alternatively, low temperature co-fired ceramic (LTCC) can be used. This multilayer technology provides high pattern resolutions in combination with high integration grades. The poor thermal conductivity of LTCC (3 to 5 W/(m-K) requires thermal vias made of silver paste which are placed between the power chip and the heat sink to reduce the thermal resistance of the substrate. The via-pitch and diameter is technologically limited, what allows a maximum filling grade of approx. 20 %. Heat spreading inside LTCC substrates is commonly realized with thick film printed metal layers which connect a smaller via matrix in the upper layer with larger via matrix in the following layer. However the heat spreading capability of these structures is limited due to the relatively low achievable metal layer thickness applying a standard screen printing process. In the presented investigation, a thick silver tape is used to form a thick silver heat spreader inside the LTCC substrate. The substrate consists of 4 layers LTCC DP951. In the top layer 36 silver vias with a diameter of 250 μm and a pitch of 500 μm are placed in a 3 × 3 mm2 substrate area. An opening is structured in the following layer by laser cutting, which is filled with a laser cut silver tape to form a 7 × 7 mm2 heat spreader. In each following layer 196 silver vias with the same pitch and diameter as the vias in the top layer are placed in a 7 × 7 mm2 area. The layers are stacked together, laminated and sintered utilizing a pressure assisted sintering process. The thermal performance of the substrate was investigated by means of simulations and measurements. A package comprising of the LTCC substrate and a thermal test chip was realized to measure the thermal performance. A thermal resistance of 2.6 K/W was evaluated for the package with integrated full metal heat spreader during these measurements. Compared to a package having a standard via structure instead of the introduced silver heat spreader a reduction of 30.5 % of the thermal resistance was achieved. Advantages of the presented heat spreader are achievable low thermal resistances ","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126941017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Preform-based diffusion soldering for use under conventional soldering process parameters","authors":"H. Daoud, S. Reichelt, A. Loidolt","doi":"10.23919/EMPC.2017.8346889","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346889","url":null,"abstract":"The diffusion soldering process has attracted much interest following the development of new wide band gap materials, such as SiC chips as well as the need to address the higher reliability requirements of emerging power electronics applications. This paper introduces novel composite materials as preforms based on diffusion soldering. The composite materials concerned consist of alternating multi-layer systems of lead-free solder and high melting point metals like Copper (Cu). The thickness of the lead-free solder layers is always less than 5 μm, whereby the total thickness of the composite material ranges from 50 μm to 300 μm. This novel composite material enables full formation of inter-metallic phases (IMPs) in the lead-free solders layers during the conventional soldering process with a short-term max. peak temperature of 250°C; (< 5 min) without using any pressure and no post-heating requirements. The re-melting temperature of the resulting structure of the composite material is higher than 400°C.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132439910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}