Optimized adaptive layout technique for hybrid systems in foil

Abstract

Compactness, cost, flexibility, and size of electronic devices play an important role for next generation consumer electronics. Flexible hybrid system in foil (HySiF) technology provides an optimum solution by combining low-cost, large and flexible organic with high circuit performance silicon [1]. In this paper, the recently published process flow of integrating micro-hybrid system in polymer foil, the so called Chip-Film Patch (CFP) based on adaptive layout, is analyzed and optimized towards increasing overlay accuracy [2]. In this matter, the overlay accuracy of adaptive layout for a wafer level embedding of chips with different thicknesses has successfully achieved measured below 1 μm in x-axis and y-axis for any arbitrary position on the embedded chip. To the best of our knowledge, this is one of the best ever achieved interconnect accuracy in assembly of thin chips in foil.