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2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification最新文献

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Motion vector and mode selection based fragile video watermarking algorithm 基于运动矢量和模式选择的脆弱视频水印算法
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967419
Gui Feng, Guojing Wu
{"title":"Motion vector and mode selection based fragile video watermarking algorithm","authors":"Gui Feng, Guojing Wu","doi":"10.1109/ASID.2011.5967419","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967419","url":null,"abstract":"According to H.264 video encoding standard, a fragile video watermark algorithm based on motion vector and mode selection is proposed. By selecting the motion vector with small splitting and minimizing the Laragian function in motion search to embed the fragile watermark into the motion vector that have the best rate distortion capability. Experimental results show that the proposed algorithm can achieve better sensitivity to the re-encoding processing and bring little influence to video quality and bit rate.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"369 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124630886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
The FPGA implement of ADPLL without retimed clock 无时钟重定时的ADPLL的FPGA实现
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967442
Shuai Jiang, Songbai He, F. You
{"title":"The FPGA implement of ADPLL without retimed clock","authors":"Shuai Jiang, Songbai He, F. You","doi":"10.1109/ASID.2011.5967442","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967442","url":null,"abstract":"A modified method to evaluate the phase of all digital phase-locked loop (ADPLL) output signal is proposed in this paper for improving the robustness property of the loop. The reference clock is used throughout the system as the synchronous clock, which can avoid the metastable output and the injection spurs caused by retiming mechanism, and differential units are added to reduce the accumulation of phase error. Besides, a time-digital converter (TDC) based loop shifting flip-flops is proposed to achieve a wide range of operation. The FPGA simulation results show that the error of frequency detector is less than 0.2‰, and the loop get into locking by 12 µs and stable in the condition of FSW=4.8.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130853328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low power design of RFID tags RFID标签的低功耗设计
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967422
X. Yao, X. Wang, J. Huang, M. Ye
{"title":"Low power design of RFID tags","authors":"X. Yao, X. Wang, J. Huang, M. Ye","doi":"10.1109/ASID.2011.5967422","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967422","url":null,"abstract":"Low-power design is essential for passive RFID tags to achieve expected level of sensitivity. Considering the mechanism of the passive tags powered, a low peak power is also important. This paper is focused on optimization on peak power. A tag IC is also presented. The IC, which is compatible with the EPC C1G2 RFID protocol, was designed and fabricated successfully by using a 0.18µm process, with a tested sensitivity of −dBm.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132702695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A two-stage amplifier with active miller compensation 具有主动米勒补偿的两级放大器
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967452
Min Tan, Qianneng Zhou
{"title":"A two-stage amplifier with active miller compensation","authors":"Min Tan, Qianneng Zhou","doi":"10.1109/ASID.2011.5967452","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967452","url":null,"abstract":"A two-stage amplifier with active miller compensation is presented in this paper. Unlike the two-stage amplifier with conventional miller compensation, the proposed structure doesn't contain right half plane zero. What is more, a left half plane zero is created to cancel the first non-dominant pole. The proposed structure improves the bandwidth significantly and reduces the dimension of the compensation capacitor. The proposed two-stage amplifier is designed and simulated in standard 0.6µm CMOS process. Simulation results show that the unit-gain frequency is increased by 9.4 times with only 38% increase in power consumption. The overall FoM is improved by 31.5 times.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115066812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A novel sub-1-V bandgap reference in 0.18µm CMOS technology 基于0.18µm CMOS技术的新型sub- 1v带隙参考
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967446
Min Tan, Fan Liu, Fei Xiang
{"title":"A novel sub-1-V bandgap reference in 0.18µm CMOS technology","authors":"Min Tan, Fan Liu, Fei Xiang","doi":"10.1109/ASID.2011.5967446","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967446","url":null,"abstract":"A sub-1-V bandgap reference in 0.18 µ m CMOS technology is introduced in this paper. A novel start-up circuitry and a novel low voltage amplifier are the enabling techniques for this design. The startup circuit consumes negligible power, yet guarantees the desired operating point of the bandgap reference. Transistors operating in sub-threshold region are used to enable sub-1-v operation of the low voltage amplifier. Unlike existing designs, the proposed amplifier can be implemented in CMOS technology with threshold voltage less than one VEB(on). The proposed sub-1-V bandgap reference is simulated in standard 0.18um CMOS technology. The maximum total current consumption is only 10.3uA and a temperature coefficient of 4.1ppm/°C can be achieved at 1.2V supply voltage. The minimum supply voltage is only 0.8V.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"42 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120921360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and implementation of FDPM in network processor 网络处理器中FDPM的设计与实现
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967434
Kunpeng Zeng, Zhongwen Li, Shan He
{"title":"Design and implementation of FDPM in network processor","authors":"Kunpeng Zeng, Zhongwen Li, Shan He","doi":"10.1109/ASID.2011.5967434","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967434","url":null,"abstract":"Notorious Distributed Denial of Service (DDoS) attacks consume a remote host or network resource to deny or degrade service to legitimate users. They have been identified as serious problems currently. Many mechanisms have been proposed to defend against DDoS attacks. IP traceback is a very important technology in these mechanisms. It provides the security system with the ability to identify the true source of the attacking IP packets. Flexible Deterministic Packet Marking (FDPM) is one of the IP traceback approaches. It only needs moderately a small number of packets to complete the IP traceback process. The implementation of FDPM in network processor demonstrates that FDPM is a good traceback method and the network processor can defend effectively against DDoS attacks.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116258393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Frontal face generation from profile face image 从侧面人脸图像生成正面人脸
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967417
Sandesh Gupta, Shashank Kapoor, Phalguni Gupta
{"title":"Frontal face generation from profile face image","authors":"Sandesh Gupta, Shashank Kapoor, Phalguni Gupta","doi":"10.1109/ASID.2011.5967417","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967417","url":null,"abstract":"This paper presents an efficient method to generate the frontal face image from the given profile face image. It uses principal component analysis (PCA) in conjunction with linear object class (LOC) method. The proposed method is tested on CMU PIE face database and it is found to be significant improvement over the well known linear object class method.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124960157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new DWT & multi-strategy watermark embedding algorithm 一种新的DWT &多策略水印嵌入算法
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967415
Qiwei Lin, JiSheng Tang, Xu-zhen Wu
{"title":"A new DWT & multi-strategy watermark embedding algorithm","authors":"Qiwei Lin, JiSheng Tang, Xu-zhen Wu","doi":"10.1109/ASID.2011.5967415","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967415","url":null,"abstract":"A novel blind digital image watermarking algorithm based on multi strategy is put forward in this paper. The watermark is embedded in multi-resolution wavelet transform domain of the original image. Based on spread spectrum techniques, the algorithm is composed of new technique to improve robustness, imperceptibility and security. In this technique, we interlace several copies of watermark in different resolution to embed in wavelet transform domain. As a result the recovered watermark is shown better performance after various attacks.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125991995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Research of real-time control algorithm for traffic lights based on CPU process scheduling 基于CPU进程调度的红绿灯实时控制算法研究
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967428
Jinrong Zhou, Xiaofang Zhou, Zhibin Chen, Xiao Chen
{"title":"Research of real-time control algorithm for traffic lights based on CPU process scheduling","authors":"Jinrong Zhou, Xiaofang Zhou, Zhibin Chen, Xiao Chen","doi":"10.1109/ASID.2011.5967428","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967428","url":null,"abstract":"To solve the problem that current transport systems cannot provide real-time response to traffic changes, this paper proposes a real-time control algorithm for traffic lights based on CPU process scheduling to reduce the waiting time of vehicles. This paper proposes a system model of implementing the real-time algorithm. First, this paper designs the appropriate hardware system based on different algorithm requirements for traffic flow information. Then extract useful information through data processing. Finally, based on different requirements for fairness and access efficiency, this paper designs five different control algorithms. The algorithm this paper proposed can support countdown-time traffic lights; it will effectively improve the efficiency of traffic.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129406154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 1.5-bit pipelined stage with time-interleaved dual-pipeline architecture used in SHA-less pipelined ADC 采用时间交错双管道架构的1.5位流水线级，用于无sha的流水线ADC
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967433
Yan Wang, Yuxin Wang, T. Liu, Ting Li, Jinbao Lan
{"title":"A 1.5-bit pipelined stage with time-interleaved dual-pipeline architecture used in SHA-less pipelined ADC","authors":"Yan Wang, Yuxin Wang, T. Liu, Ting Li, Jinbao Lan","doi":"10.1109/ASID.2011.5967433","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967433","url":null,"abstract":"A design of a 1.5-bit pipelined stage with time-interleaved dual-pipeline architecture used in SHA-less pipelined ADC is presented in this paper. Due to the absence of SHA, sampling flash architecture and bootstrapped sampling switch is used to improve the linearity. Op-amp sharing between time-interleaved dual-pipeline is to reduce power consumption. The sampling network is specially analyzed. The pipelined stage can be used as the first stage of a 10-bit 40 MHz pipelined A/D converter. Simulation by Spectra on 0.18um CMOS process under 1.8V supply voltage shows its SFDR achieves 62 dB near Nyquist input frequency.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125076774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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