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2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification最新文献

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Formation of checkerboard patterns in one-dimensional computational verb cellular networks 一维计算动词细胞网络中棋盘模式的形成
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967416
Xiaoli Lin, Tao Yang
{"title":"Formation of checkerboard patterns in one-dimensional computational verb cellular networks","authors":"Xiaoli Lin, Tao Yang","doi":"10.1109/ASID.2011.5967416","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967416","url":null,"abstract":"Computational verb cellular network (CVCN) is a new kind of cellular computational platform where the local rules are computational verb rules. In this paper, the mechanism of forming checkerboard patterns in one-dimensional CVCN (1D CVCN) is studied mathematically. Three conditions of generating checkerboard patterns are proved mathematically based on the decomposition of global evolving patterns.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126158264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Computational verb similarity between verbs with distortions of time 具有时间扭曲的动词之间的计算动词相似性
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967420
Juanjuan Sun, Tao Yang
{"title":"Computational verb similarity between verbs with distortions of time","authors":"Juanjuan Sun, Tao Yang","doi":"10.1109/ASID.2011.5967420","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967420","url":null,"abstract":"Computational verb similarities(CVS) play critical roles in researches and applications of computational verb theory. In the existing literature, CVS was mainly calculated between two computational verbs, of which the life spans are the same. In this paper, by taking advantages of different data processing algorithms, the methods of calculating the CVS between computational verbs of which the life spans are different and the time axis is subjected to distortions.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114883509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A current switch of current-steering DAC output stage 电流控制DAC输出级的电流开关
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967439
Pu Luo, Weidong Yang, D. Fu
{"title":"A current switch of current-steering DAC output stage","authors":"Pu Luo, Weidong Yang, D. Fu","doi":"10.1109/ASID.2011.5967439","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967439","url":null,"abstract":"When DAC is applied to communication field, it is generally necessary to have a good dynamic performance. However, nonlinear distortion of output stage current switch has a potent effect on DAC as a whole. The approach proposed in this paper aims to improve on distortion in output stage. As a result of practical measurement, clock frequency is 200MHz, and SFDR of the DAC with a data frequency of 20MHz is 83dBC.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122612454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The mechanism to control file-pollution based on hybrid trust-model in P2P network 基于混合信任模型的P2P网络文件污染控制机制
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967407
Zhongwen Li, Jingjing Yao, Liang Shi
{"title":"The mechanism to control file-pollution based on hybrid trust-model in P2P network","authors":"Zhongwen Li, Jingjing Yao, Liang Shi","doi":"10.1109/ASID.2011.5967407","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967407","url":null,"abstract":"File-pollution, which results in all kinds of malicious and unavailable files, such as Trojan, Sirius, into the network, is a common phenomenon. However, it decreases availability of files in network, threatens security of peers, badly hinders the development of P2P file-sharing network. Nowadays, research on file-pollution still focus on mathematical mode and observation of file-pollution on main popular P2P file-sharing network, and don't refer to effective anti-pollution mechanism. By considering impact of peers' behaviors to file-pollution, PFtrust mode was proposed. It not only restricts behavior of peers, but also identifies quality of contaminated files. Compared to other credit-based scheme, PFtrust performs much better in three aspects: convergence rate, speed to clean up contaminated file and speed to isolate malicious peer, which represents that it's an effective mechanism to control file-pollution.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123133568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The 10 GHz wide tuning and low phase-noise PLL chip design 10ghz宽调谐低相位噪声锁相环芯片设计
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967440
Jhin-Fang Huang, C. Mao, Ron-Yi Liu
{"title":"The 10 GHz wide tuning and low phase-noise PLL chip design","authors":"Jhin-Fang Huang, C. Mao, Ron-Yi Liu","doi":"10.1109/ASID.2011.5967440","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967440","url":null,"abstract":"An integer-N phase-locked loop (PLL) operating at 10 GHz is designed and fabricated in TSMC 0.18-um CMOS technology. The proposed PLL with a LC-tank voltage-controlled oscillator (VCO) and a mixed design of current mode logic (CML) and true single phase clock (TSPC) logic in the frequency divider achieves a tuning range from 8.75 GHz to 10.93 GHz and a phase noise of −113.4 dBc per Hertz at an offset frequency of 1 MHz from the carry frequency of 10.49 GHz. The final simulated locking time is lower than 3.7 us. Including pads and an on-chip third-order low-pass filter, the overall chip area is only 0.82×0.68 mm2 (0.56 mm2) as well as the power consumption is 39 mW at the 1.8 V supply voltage.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124425860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A fast GPU-based implementation for MD5 hash reverse 基于gpu的MD5哈希反向快速实现
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967405
Hongwei Wu, Xiangnan Liu, W. Tang
{"title":"A fast GPU-based implementation for MD5 hash reverse","authors":"Hongwei Wu, Xiangnan Liu, W. Tang","doi":"10.1109/ASID.2011.5967405","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967405","url":null,"abstract":"Thanks to the development of hardware technology, the Graphics Processing Unit (GPU), as a highly parallel programmable processor, has been applied to more and more advanced mainstream computing systems. In this paper, some optimizations for Message-Digest algorithm 5(MD5) hash reverse were presented, which have been implemented on a GPU parallel architecture called CUDA. The performance of our solution is compared with the implementation running on an AMD II X4 945 four core CPU running at 3.0GHz, and the result shows that our GPU-based MD5 hash reverse implementation is more than ten times faster than an optimized CPU implementation.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131901847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Design of low power low noise amplifier for portable electrocardiogram recording system applications 便携式心电图记录系统用低功耗低噪声放大器的设计
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967423
Xiao Yang, Qi Cheng, Li-fei Lin, Wei-wei Huang, Chao-dong Ling
{"title":"Design of low power low noise amplifier for portable electrocardiogram recording system applications","authors":"Xiao Yang, Qi Cheng, Li-fei Lin, Wei-wei Huang, Chao-dong Ling","doi":"10.1109/ASID.2011.5967423","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967423","url":null,"abstract":"Electrocardiogram (ECG) signals have the characteristics of low amplitude and low frequency. A low-power, low-noise and low voltage amplifier is required for long term ECG signals monitoring. Chopping technique is an efficient approach to decrease the 1/f noise of CMOS amplifiers, but conventional chopper amplifier consumes large power because it required a wide-band amplifier exceed chopping frequency and a post low-pass filter to filter modulation noise. Moreover, the DC offset created by skin-electrode interface can reach as high as ±100mV and can easily saturate the amplifier, which limits the amount of gain applied to amplifiers. In this paper, an amplifier with low power, low noise and electrode dc offset suppression is presented for ECG recording system applications. The main amplifier is a chopper amplifier without post low-pass filter, which can reduce power consumption. The complete amplifier configured with the low power chopper amplifier can suppress the electrode dc offset effectively. The circuit of the presented amplifier is designed in TSMC 0.18µm 1P4M CMOS process. The achieved input integrated referred noise voltage is 0.68µV rms from 0.1Hz to 150Hz with high CMRR of 107dB. The power consumption is 46.8 µW with µ0.9V supply.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116569494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A bandgap voltage reference design for high power supply 大功率电源带隙基准电压设计
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967447
Wei-wei Huang, Xiao Yang, Chao-dong Ling
{"title":"A bandgap voltage reference design for high power supply","authors":"Wei-wei Huang, Xiao Yang, Chao-dong Ling","doi":"10.1109/ASID.2011.5967447","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967447","url":null,"abstract":"Based on the CSMC 0.6um 40V BCD process and the bandgap principle a reference circuit used in high voltage chip is designed. The simulation results show that a temperature coefficient of 26.5ppm/°C in the range of 3.5∼40V supply, the output voltage is insensitive to the power supply, when the supply voltage rages from 3.5∼40V, the output voltage is equal to 1.2558V to 1.2573V at room temperature. The circuit we designed has high precision and stability, thus it can be used as stability reference voltage in power management IC.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124081324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
3D image skeleton algorithms 三维图像骨架算法
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967425
Jiangui Wu, H. Duan, Qi Zhong
{"title":"3D image skeleton algorithms","authors":"Jiangui Wu, H. Duan, Qi Zhong","doi":"10.1109/ASID.2011.5967425","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967425","url":null,"abstract":"Skeletons are “compact” representations of the original objects, which are useful for many visualization tasks including medical imaging, computer graphics, computer-aided design. We introduce the basic concepts and properties of 3D skeletonization in this paper. Then we present the techniques of 3D skeletonization, especially in thinning. We also discuss the problems confronted in this field.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124217882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 12-Bit high-speed ADC based on GeSi BiCMOS process 一种基于GeSi BiCMOS工艺的12位高速ADC
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI: 10.1109/ASID.2011.5967437
L. Li, Xingfa Huang, Mingyuan Xu
{"title":"A 12-Bit high-speed ADC based on GeSi BiCMOS process","authors":"L. Li, Xingfa Huang, Mingyuan Xu","doi":"10.1109/ASID.2011.5967437","DOIUrl":"https://doi.org/10.1109/ASID.2011.5967437","url":null,"abstract":"In this paper, a 7 stage switched capacitor pipelined ADC is described. This ADC is designed to achieve 12-bit resolution at the speed up to 125MSPS, which uses a fully differential switched capacitor pipelined architecture. This ADC includes an input broadband buffer, which isolates the ADC from external driver circuit, a high performance sample-and-hold amplifier (SHA) front end, and 7 pipelined sub-ADC stages to achieve 12-bit accuracy. A double poly triple metal 0.35µm GeSi BiCMOS process with 5V analog power supply is used in the design. This ADC achieves an SNR of 66dB and an SFDR of 80dB for sampling analog input frequencies up to 50MHz.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127300169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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