{"title":"具有主动米勒补偿的两级放大器","authors":"Min Tan, Qianneng Zhou","doi":"10.1109/ASID.2011.5967452","DOIUrl":null,"url":null,"abstract":"A two-stage amplifier with active miller compensation is presented in this paper. Unlike the two-stage amplifier with conventional miller compensation, the proposed structure doesn't contain right half plane zero. What is more, a left half plane zero is created to cancel the first non-dominant pole. The proposed structure improves the bandwidth significantly and reduces the dimension of the compensation capacitor. The proposed two-stage amplifier is designed and simulated in standard 0.6µm CMOS process. Simulation results show that the unit-gain frequency is increased by 9.4 times with only 38% increase in power consumption. The overall FoM is improved by 31.5 times.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A two-stage amplifier with active miller compensation\",\"authors\":\"Min Tan, Qianneng Zhou\",\"doi\":\"10.1109/ASID.2011.5967452\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A two-stage amplifier with active miller compensation is presented in this paper. Unlike the two-stage amplifier with conventional miller compensation, the proposed structure doesn't contain right half plane zero. What is more, a left half plane zero is created to cancel the first non-dominant pole. The proposed structure improves the bandwidth significantly and reduces the dimension of the compensation capacitor. The proposed two-stage amplifier is designed and simulated in standard 0.6µm CMOS process. Simulation results show that the unit-gain frequency is increased by 9.4 times with only 38% increase in power consumption. The overall FoM is improved by 31.5 times.\",\"PeriodicalId\":328792,\"journal\":{\"name\":\"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASID.2011.5967452\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASID.2011.5967452","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A two-stage amplifier with active miller compensation
A two-stage amplifier with active miller compensation is presented in this paper. Unlike the two-stage amplifier with conventional miller compensation, the proposed structure doesn't contain right half plane zero. What is more, a left half plane zero is created to cancel the first non-dominant pole. The proposed structure improves the bandwidth significantly and reduces the dimension of the compensation capacitor. The proposed two-stage amplifier is designed and simulated in standard 0.6µm CMOS process. Simulation results show that the unit-gain frequency is increased by 9.4 times with only 38% increase in power consumption. The overall FoM is improved by 31.5 times.