Low power design of RFID tags

2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI:10.1109/ASID.2011.5967422

X. Yao, X. Wang, J. Huang, M. Ye

引用次数: 1

Abstract

Low-power design is essential for passive RFID tags to achieve expected level of sensitivity. Considering the mechanism of the passive tags powered, a low peak power is also important. This paper is focused on optimization on peak power. A tag IC is also presented. The IC, which is compatible with the EPC C1G2 RFID protocol, was designed and fabricated successfully by using a 0.18µm process, with a tested sensitivity of −dBm.

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RFID标签的低功耗设计

低功耗设计对于无源RFID标签达到预期的灵敏度水平至关重要。考虑到无源标签供电的机制，低峰值功率也很重要。本文重点研究了峰值功率的优化问题。并提出了一种标签集成电路。该IC兼容EPC C1G2 RFID协议，采用0.18µm工艺，测试灵敏度为−dBm。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification

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