A 1.5-bit pipelined stage with time-interleaved dual-pipeline architecture used in SHA-less pipelined ADC

Abstract

A design of a 1.5-bit pipelined stage with time-interleaved dual-pipeline architecture used in SHA-less pipelined ADC is presented in this paper. Due to the absence of SHA, sampling flash architecture and bootstrapped sampling switch is used to improve the linearity. Op-amp sharing between time-interleaved dual-pipeline is to reduce power consumption. The sampling network is specially analyzed. The pipelined stage can be used as the first stage of a 10-bit 40 MHz pipelined A/D converter. Simulation by Spectra on 0.18um CMOS process under 1.8V supply voltage shows its SFDR achieves 62 dB near Nyquist input frequency.