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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)最新文献

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Improved wideband low distortion cascaded delta-sigma modulator 改进的宽带低失真级联δ - σ调制器
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.75
Xiaolong Yuan, A. Gothenberg, Xiaobo Wu
{"title":"Improved wideband low distortion cascaded delta-sigma modulator","authors":"Xiaolong Yuan, A. Gothenberg, Xiaobo Wu","doi":"10.1109/IWSOC.2005.75","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.75","url":null,"abstract":"It has recently become very popular to feedforward the input signal in wideband delta-sigma modulators, so that the integrators only process quantization errors. The advantage being that the actual signal is not distorted by opamp and integrator nonlinearities. In this paper, we focus on improved feedforward techniques for cascaded delta-sigma modulators. A feedforward cascaded structure is presented based on unity-gain signal transfer function (STF) and optimized noise transfer function (NTF) zero placement, using /spl lambda/-analysis. The proposed structure has improved signal-to-noise-ratio (SNR) across the entire input range.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114147315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modular architecture for system-on-chip design of scalable MEMS optical switch actuator controller 基于模块化架构的可扩展MEMS光开关执行器控制器片上系统设计
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.84
Xiqun Zhu, Yuan Ma
{"title":"Modular architecture for system-on-chip design of scalable MEMS optical switch actuator controller","authors":"Xiqun Zhu, Yuan Ma","doi":"10.1109/IWSOC.2005.84","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.84","url":null,"abstract":"In this paper, a modular architecture for system-on-chip design of scalable embedded MEMS actuator controller is presented. It addresses the contradiction between often large and expanding system function requirements and limited system resources, and provides a system level solution to solve this contradiction. A design methodology is developed to break the system function into multiple self-contained modules in case the above contradiction can not be solved in single chip design. A simple adaptive inter-modules/chip communications protocol is presented to maintain system integrity when modules/chips are added or removed.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114238480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An automatic layout generator for I/O cells I/O单元的自动布局生成器
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.39
Li-Chun Tien, Jing-Jou Tang, Mi-Chang Chang
{"title":"An automatic layout generator for I/O cells","authors":"Li-Chun Tien, Jing-Jou Tang, Mi-Chang Chang","doi":"10.1109/IWSOC.2005.39","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.39","url":null,"abstract":"We present a design methodology for I/O cell library design automation. It's different from the conventional cell library compilers or generators, which generate the cells for standard cells or regular structures (e.g., SRAM). The proposed compiler generates I/O cells based on a set of parameterized unit-cells with the features of scalable geometry dependence. The compilation results of the I/O cells have been proved in a 0.13 /spl mu/m LOGIC IP8M process. Through this compiler, the number of unit-cells needed to be maintained is dramatically reduced, thereby reducing library development costs and time to market.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125398622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A very low-power flash A/D converter based on CMOS inverter circuit 一种基于CMOS逆变电路的极低功耗闪存A/D转换器
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.33
Shih-Chang Hsia, Wen-Ching Lee
{"title":"A very low-power flash A/D converter based on CMOS inverter circuit","authors":"Shih-Chang Hsia, Wen-Ching Lee","doi":"10.1109/IWSOC.2005.33","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.33","url":null,"abstract":"A/D converter (ADC) is a basic device in digital signal processing systems. For high-speed applications, a flash ADC type is often used. Due to require many analog comparators, the chip complexity and power dissipation become very high. Moreover, the accuracy of dividing resistors requires very high for reference voltage if the converting resolution is high. In this study, we develop a new kind of flash ADC based on a simple CMOS circuit. By adjusting the ratio of channel length and width, the transition threshold of the CMOS inverters is various to detect input analog signal. Then their results are encoded to the digital code. The advantages are that the ADC circuit does not need any resistor and use simple CMOS inverters rather than analog comparators. The new 8-bit ADC chip only used 634 transistors. The power dissipates 0.9mW using 0.35/spl mu/m process when it operates at 100MHz.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126080935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A hardware-accelerated framework with IP-blocks for application in MPEG-4 在MPEG-4中应用的带有ip块的硬件加速框架
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.10
I. Amer, C. A. Rahman, T. Mohamed, M. Sayed, Wael Badawy
{"title":"A hardware-accelerated framework with IP-blocks for application in MPEG-4","authors":"I. Amer, C. A. Rahman, T. Mohamed, M. Sayed, Wael Badawy","doi":"10.1109/IWSOC.2005.10","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.10","url":null,"abstract":"In this paper we present a hardware-accelerated framework and hardware blocks for MPEG-4 part 10 IP-quality assessment. We give examples of various IP-blocks that have been designed and tested on the integration platform. The hardware-accelerated framework enabled us to asses their quality along with the MPEG-4 part 10 software reference model.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126048169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A scalable low power imager architecture for compound-eye vision sensors 一种用于复眼视觉传感器的可扩展低功耗成像仪架构
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.26
F. Boussaïd, Shoushun Chen, A. Bermak
{"title":"A scalable low power imager architecture for compound-eye vision sensors","authors":"F. Boussaïd, Shoushun Chen, A. Bermak","doi":"10.1109/IWSOC.2005.26","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.26","url":null,"abstract":"In this paper, we propose a scalable low power imager architecture for compound-eye vision sensors. The proposed hardware architecture is based on a time domain data representation as well as a biologically inspired read-out strategy using address-event-representation (AER). The proposed AER approach to compound-eye imaging enables low power operation (10nA/pixel), efficient read-out, improved signal-to-noise ratio together with wide dynamic range. Moreover, the proposed AER-based VLSI architecture is scalable and well suited to the next generation of deep submicron silicon processes owing to decreased supply voltage, process variability and increased noise levels.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122739926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-power programmable signal processing 低功耗可编程信号处理
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.83
P. Hasler
{"title":"Low-power programmable signal processing","authors":"P. Hasler","doi":"10.1109/IWSOC.2005.83","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.83","url":null,"abstract":"This paper presents the potential of using programmable analog signal processing techniques for impacting low-power portable applications like imaging, audio processing, and speech recognition. The range of analog signal processing functions available results in many potential opportunities to incorporate these analog signal processing systems with digital signal processing systems for improved overall system performance. Programmable, dense analog techniques enable these approaches, based upon programmable transistor approaches. We show experimental evidence for the factor of 1000 to 10,000 power efficiency improvement for programmable analog signal processing compared to custom digital implementations in vector matrix multipliers (VMM), CMOS imagers with computation on the pixel plane with high fill factors, and large-scale field programmable analog arrays (FPAA), among others.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123280196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
System on chip: challenges and design for manufacturing 片上系统:制造业的挑战与设计
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.101
A. Nezar, Michael Creighton
{"title":"System on chip: challenges and design for manufacturing","authors":"A. Nezar, Michael Creighton","doi":"10.1109/IWSOC.2005.101","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.101","url":null,"abstract":"Advances in lithography, semiconductor processes and circuit design techniques have led to new opportunities to integrate most of the electronic functions encountered in systems. This single-chip solution (SoC) includes functions such as digital signal processing (DSP), memory, microcontrollers and wireless transceivers, enabling the system to communicate with other systems and the Internet. This multi-disciplinary approach calls for increasing design for manufacturing (DFM) synergy to enable all the functions without compromising functionality and performance of each function.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124640825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Enabling technology for analog integration 使能模拟集成技术
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.56
P. Kempf
{"title":"Enabling technology for analog integration","authors":"P. Kempf","doi":"10.1109/IWSOC.2005.56","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.56","url":null,"abstract":"Summary form only given. The semiconductor industry has recently been emphasizing a trend toward integration of precision analog and RF circuitry in CMOS for system-level chips, but is currently encountering significant obstacles in realizing this goal. Growth is rampant in the number and type of RF interfaces required to support voice, data, positioning, video, television and radio in portable devices. Complexity in the analog/RF sub-system begs for technology solutions that enable flexible implementation of new features without compromising performance and time-to-market. The industry roadmap does not provide a viable technology path for single chip integration of all analog blocks in advanced geometry CMOS, so while the digital sub-system absorbs the signal processing requirements for new networking and multi-media functions, the entire analog sub-system remains as the next opportunity for integration.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131073481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and optimization of low-voltage low-power quasi-floating gate digital circuits 低压低功耗准浮门数字电路的设计与优化
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.49
K. Townsend, J. Haslett, K. Iniewski
{"title":"Design and optimization of low-voltage low-power quasi-floating gate digital circuits","authors":"K. Townsend, J. Haslett, K. Iniewski","doi":"10.1109/IWSOC.2005.49","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.49","url":null,"abstract":"This paper explores the design and optimization of quasi-floating gate MOS techniques to low-voltage/low-power digital circuitry. The simulated power consumption of standard CMOS gates is compared to that of QFGMOS implementations in a 0.18/spl mu/m process for different supply voltages and device sizes. A 0.4V V/sub DD/ full-adder biased for propagation delay similar to that of 0.8V CMOS is simulated and shown to consume 1.2/spl mu/W for a 50MHz input, representing more than a 50% power reduction over the CMOS equivalent. A divide-by-16 circuit designed for operation at a maximum frequency of 400MHz uses 25/spl mu/W, 45/spl mu/W, and 75/spl mu/W for supplies of 0.4V, 0.6V and 0.8V.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133877390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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