A hardware-accelerated framework with IP-blocks for application in MPEG-4

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI:10.1109/IWSOC.2005.10

I. Amer, C. A. Rahman, T. Mohamed, M. Sayed, Wael Badawy

引用次数: 15

Abstract

In this paper we present a hardware-accelerated framework and hardware blocks for MPEG-4 part 10 IP-quality assessment. We give examples of various IP-blocks that have been designed and tested on the integration platform. The hardware-accelerated framework enabled us to asses their quality along with the MPEG-4 part 10 software reference model.

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在MPEG-4中应用的带有ip块的硬件加速框架

本文提出了一种用于MPEG-4 part 10 ip质量评估的硬件加速框架和硬件模块。我们给出了在集成平台上设计和测试的各种ip块的示例。硬件加速框架使我们能够与MPEG-4 part 10软件参考模型一起评估它们的质量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

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