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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)最新文献

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A new topology for power control of high efficiency class-E switched mode power amplifier 一种高效率e类开关模式功率放大器功率控制的新拓扑
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.18
M. M. Tabriz, N. Masoumi
{"title":"A new topology for power control of high efficiency class-E switched mode power amplifier","authors":"M. M. Tabriz, N. Masoumi","doi":"10.1109/IWSOC.2005.18","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.18","url":null,"abstract":"This paper presents a new methodology for improving overall efficiency of class-E power amplifiers. Power amplifiers are designed for maximum efficiency at the highest output power, while the efficiency decreases as the output power reduces. To achieve a long battery life and block interference, output power must be controlled based on the distance between a transmitter and a receiver. This new methodology employs optimized circuit topology in power control circuit in order to have small drop in efficiency at low output power. The proposed circuit is simulated using Hspice in 0.25 /spl mu/m CMOS technology as well as ADS lumped model of spiral inductors is employed. The results indicate that the efficiency reduces about 40% when the power amplifier operates at 10% of the maximum output power.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129689953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Leakage current variability in nanometer technologies 纳米技术中的泄漏电流变异性
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.78
M. Anis, M. Abu-Rahma
{"title":"Leakage current variability in nanometer technologies","authors":"M. Anis, M. Abu-Rahma","doi":"10.1109/IWSOC.2005.78","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.78","url":null,"abstract":"The dramatic increase in leakage current coupled with the large increase in variability in highly scaled CMOS technologies, pose a major challenge for future IC design. Leakage variability can not be neglected any more, due to the increase of leakage power percentage in modern ICs. In this paper, the main sources of variations and how they impact leakage current are discussed. Design guidelines to reduce variability based on several leakage reduction techniques are also presented. It is shown that reverse body bias technique increases leakage variability due to its deteriorating effect on drain-induced barrier lowering (DIBL). This paper highlights the need for further efforts in the area of statistical leakage estimation, as well as variation tolerant circuit techniques.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130059233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A review of common receive-end adaptive equalization schemes and algorithms for a high-speed serial backplane 高速串行背板常用的接收端自适应均衡方案和算法综述
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.24
Charles E. Berndt, T. Kwasniewski
{"title":"A review of common receive-end adaptive equalization schemes and algorithms for a high-speed serial backplane","authors":"Charles E. Berndt, T. Kwasniewski","doi":"10.1109/IWSOC.2005.24","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.24","url":null,"abstract":"This paper provides a review of the structures and algorithms used in receive end adaptive equalization. These structures are necessary in order to allow high speed signaling over several gigabits per second across a serial backplane channel. As the data rates continue to increase over these channels the causes and the techniques used mitigate interference become more and more important.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125453803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A power efficient decoder for 2GHz, 6-bit CMOS flash-ADC architecture 为2GHz, 6位CMOS闪存- adc架构的低功耗解码器
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.22
Syed Masood Ali, R. Raut, M. Sawan
{"title":"A power efficient decoder for 2GHz, 6-bit CMOS flash-ADC architecture","authors":"Syed Masood Ali, R. Raut, M. Sawan","doi":"10.1109/IWSOC.2005.22","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.22","url":null,"abstract":"The thermometer code to binary code (TC-to-BC) decoder is found to be one of the major limitations for flash type ADCs to perform satisfactorily for ultra high speed operations with minimum power dissipation. The authors propose a solution based on current mode approach to implement a neural network based parallel ADC-decoder that is suitable for both system-on-chip and off-chip applications. The successful implementation is being presented for a 6-bit, 2GHz, with less than 19mW average power dissipation. The design was simulated using Cadence Spectre in a standard TSMC 0.18/spl mu/m technology.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124436573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Turbo codes - digital IC design Turbo码-数字集成电路设计
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.109
Moeed Israr, T. Kwasniewski
{"title":"Turbo codes - digital IC design","authors":"Moeed Israr, T. Kwasniewski","doi":"10.1109/IWSOC.2005.109","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.109","url":null,"abstract":"This paper presents a digital ASIC implementation of turbo encoder and simulation of the encoder and the decoder. The simulations determine the impact of decoder iterations, encoder transfer function and block size on latency, throughput and bit error rate. The paper proposes a design of turbo encoding hardware with dual-port on-chip memory targeting 0.18 /spl mu/m CMOS technology that reduces the memory requirements to half architectural and block level consideration are made to reduce power and area requirements while achieving a latency of \"packet size + 5\" clock cycles. Estimated power and area are 54.19mW and 12.0 mm/sup 2/ respectively.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127904238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Synchronous pipelined relay stations with back-pressure tolerance 具有背压容忍度的同步流水线中继站
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.100
R. Su, R. Mittal, V. Garg
{"title":"Synchronous pipelined relay stations with back-pressure tolerance","authors":"R. Su, R. Mittal, V. Garg","doi":"10.1109/IWSOC.2005.100","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.100","url":null,"abstract":"Deep submicron technologies are causing interconnect delays to become a larger fraction of the clock cycle time. A solution to this problem is to pipeline the long wire in order to increase channel throughput and maintain an acceptable clock frequency. The delay of the interconnect is distributed over several clock cycles by inserting relay stations which allow for fully synchronous operation at a higher frequency. We discuss a relay station scheme that takes advantage of storage in the interconnect to minimize system stalls. We also discuss various implementation issues and design choices, such as clock gating. Additionally, we present the results of a system-on-chip crossbar, which we designed to utilize these modules. We believe that this type of approach is crucial for maintaining the overall improvement of performance in future systems and technologies.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127630524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An FPGA design of a unified hash engine for IPSec authentication 一种用于IPSec认证的统一哈希引擎FPGA设计
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.41
E. Khan, M. El-Kharashi, F. Gebali, M. Abd-El-Barr
{"title":"An FPGA design of a unified hash engine for IPSec authentication","authors":"E. Khan, M. El-Kharashi, F. Gebali, M. Abd-El-Barr","doi":"10.1109/IWSOC.2005.41","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.41","url":null,"abstract":"Hash functions are important security primitives used for authentication and data integrity. Among the most popular hash functions are MD5, SHA-1, and RIPEMD-160 that are used in conjunction with HMAC for IPSec. These three hash functions are based on an older one, MD4. Therefore, they have some similarities that can be exploited for designing a unified engine to perform the three hash functions. A unified engine design proves useful since the three algorithms are to be used by same implementation on the same core for authentication and data integrity using HMAC for IPSec. In this work, we design a SoC with a unified hash engine that can be reconfigured at runtime to perform one of the three hash functions. The results of our work show that the proposed engine has a balance between area and throughput compared to previous works.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131341843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Programmable low dropout voltage regulator 可编程低差电压调节器
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.95
P. Hasler, A. Low
{"title":"Programmable low dropout voltage regulator","authors":"P. Hasler, A. Low","doi":"10.1109/IWSOC.2005.95","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.95","url":null,"abstract":"We present a design for a low dropout (LDO) voltage regulator is presented using floating-gate techniques to set the regulator output voltage and the ac and dc operating points of the circuit. In comparison with conventional topologies, this approach does not require a feedback resistive divider or a bandgap reference to generate a temperature independent voltage. The use of floating-gates allows the regulator output to be programmed to a desired mode of operation and then stored in a non-volatile manner. Experimental results are presented from a prototype circuit fabricated in MOSIS; this circuit has been functional in 2.0/spl mu/m, 1.2/spl mu/m, and 0.5/spl mu/m processes available through MOSIS.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131818193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
VHDL simulation and modeling of an all-digital RF transmitter 全数字射频发射机的VHDL仿真与建模
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.112
R. Staszewski, R. Staszewski, P. Balsara
{"title":"VHDL simulation and modeling of an all-digital RF transmitter","authors":"R. Staszewski, R. Staszewski, P. Balsara","doi":"10.1109/IWSOC.2005.112","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.112","url":null,"abstract":"We describe a simulation technique that uses an event-driven VHDL simulator to model an RF wireless transmitter. The technique is well suited to investigate complex interactions in large SoC systems, where traditional RF and analog simulation tools do not work effectively. The oscillator phase noise characteristics are described using time-domain equations. The flip-flop metastability effects on the system performance are also modeled. The VHDL simulation environment was selected for its high simulation speed, the direct correlation between the simulated and built circuits and its ability to model mixed-signal systems of high complexity. The presented simulation technique has been successfully applied and validated in a single-chip GSM/EDGE transceiver IC fabricated in a digital 90 nm process.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124434818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Recent advances and future trends in low power wireless systems for medical applications 医疗应用低功耗无线系统的最新进展和未来趋势
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.96
K. Townsend, J. Haslett, T. Tsang, M. El-Gamal, K. Iniewski
{"title":"Recent advances and future trends in low power wireless systems for medical applications","authors":"K. Townsend, J. Haslett, T. Tsang, M. El-Gamal, K. Iniewski","doi":"10.1109/IWSOC.2005.96","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.96","url":null,"abstract":"This paper describes current state-of-the-art research on low power wireless systems for medical applications. Distinct design criteria and challenges in this area are addressed. A study of existing wireless technologies and their key applications are presented. A brief assessment of future trends for wireless medicine with a focus on emerging technologies is provided. Finally, a number of different energy-scavenging techniques for the future development of autonomous wireless nodes are reviewed.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128451029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
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