A power efficient decoder for 2GHz, 6-bit CMOS flash-ADC architecture

Abstract

The thermometer code to binary code (TC-to-BC) decoder is found to be one of the major limitations for flash type ADCs to perform satisfactorily for ultra high speed operations with minimum power dissipation. The authors propose a solution based on current mode approach to implement a neural network based parallel ADC-decoder that is suitable for both system-on-chip and off-chip applications. The successful implementation is being presented for a 6-bit, 2GHz, with less than 19mW average power dissipation. The design was simulated using Cadence Spectre in a standard TSMC 0.18/spl mu/m technology.