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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)最新文献

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Three dimensional system on chip technology 片上三维系统技术
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.106
E. Swartzlander
{"title":"Three dimensional system on chip technology","authors":"E. Swartzlander","doi":"10.1109/IWSOC.2005.106","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.106","url":null,"abstract":"With ever-finer device geometry, increasing device counts and interconnect delays playing a larger role in the performance of a system on a chip, the architectures that are used to support such technologies must take these factors into account. Highly pipelined or highly parallel architectures that utilize local processing, and therefore shorter interconnects, are required. Three-dimensional, monolithic integrated circuit technology which can significantly shorten the interconnects and accommodate more devices per chip may be an attractive solution. The basic idea is presented along with an illustrative application specific processor design.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121720753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hardware acceleration of deadlock avoidance and detection in real-time operating systems 实时操作系统中死锁避免和检测的硬件加速
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.70
P. Samson, P. Sinha
{"title":"Hardware acceleration of deadlock avoidance and detection in real-time operating systems","authors":"P. Samson, P. Sinha","doi":"10.1109/IWSOC.2005.70","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.70","url":null,"abstract":"In a multitasking environment, resource management policies, being devised and utilized to ensure proper inter-process resource sharing, incur significant operational overhead due to their inherent complexity and often lead to performance penalties, which could be detrimental to the timing responses of critical systems. In this paper, we propose and demonstrate an approach to alleviate degraded system's timing performance by associating the underlying RTOS with a hardware accelerator to speed up resource management functions, more particularly those dealing with deadlock avoidance. Experimentally, the proposed solution for deadlock avoidance surpasses its software implementation with an acceleration gain of up to 98 %.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134165851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transaction analysis of multiprocessor based platform with bus matrix 基于总线矩阵的多处理器平台事务分析
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.108
Seungbeom Lee, Sin-Chong Park
{"title":"Transaction analysis of multiprocessor based platform with bus matrix","authors":"Seungbeom Lee, Sin-Chong Park","doi":"10.1109/IWSOC.2005.108","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.108","url":null,"abstract":"This paper presents an analysis of transaction of multiprocessor platform with bus matrix. Simple equations about the latency and throughput for this architecture are derived. From this equation we evaluate operating frequency to meet latency and throughput requirements. This architecture is modeled as transaction level model (TLM) in SystemC in order to confirm the validation of the governing equation. The result of simulation corresponds to that of the derived equation.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132965636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
System-level analog simulation of a mixed-signal continuous-time field programmable analog array 混合信号连续时间现场可编程模拟阵列的系统级模拟仿真
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.102
J. Becker, F. Henrici, Y. Manoli
{"title":"System-level analog simulation of a mixed-signal continuous-time field programmable analog array","authors":"J. Becker, F. Henrici, Y. Manoli","doi":"10.1109/IWSOC.2005.102","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.102","url":null,"abstract":"Field programmable analog arrays (FPAAs) represent analog signal transfer functions, which depend on alterable digital configuration data. They are indispensable if reconfigurable analog signal processing has to be included in a system-on-chip. For system-level design of filter structures as well as accurate transistor-level simulations of the analog transfer function, it is necessary to enter the respective configuration data before phase/magnitude analyses are run. This paper introduces a graphical design-entry tool for an FPAA consisting of 17 g/sub m/-C blocks for instantiation of high-frequency filters. It also reports on first simulation results confirming the feasibility up to corner frequencies of hundreds of MHz. Transfer function simulations of basic building-blocks are compared with theory and lead to an exemplary instantiation of a fourth-order Butterworth-filter.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130863227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A generic method for embedded measurement and compensation of process and temperature variations in SOCs 一个通用的方法嵌入式测量和补偿过程和温度变化的soc
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.9
H. Bui, Y. Savaria
{"title":"A generic method for embedded measurement and compensation of process and temperature variations in SOCs","authors":"H. Bui, Y. Savaria","doi":"10.1109/IWSOC.2005.9","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.9","url":null,"abstract":"This paper proposes an embedded method of measuring process and temperature variations using the resulting change in transconductance of affected transistors. It also presents a compensation scheme for these variations using a generic and versatile method that can conveniently be used in system-on-chip applications. The measuring and compensating system has been applied on a 9-stage current-controlled oscillator. Differences in oscillating frequency between corner cases have been reduced from over 90 MHz to less than 10 MHz.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"13 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131848565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Power reduction technique using multi-Vt libraries 使用多vt库的功率降低技术
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.92
Meeta Srivastav, S. Rao, Himanshu Bhatnagar
{"title":"Power reduction technique using multi-Vt libraries","authors":"Meeta Srivastav, S. Rao, Himanshu Bhatnagar","doi":"10.1109/IWSOC.2005.92","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.92","url":null,"abstract":"In DSM technology leakage power dissipation in a cell becomes significant. Due to this significant rise in leakage power some measures should be taken quite early in the design flow to reduce it rather than realizing it later and either increasing the time to market by increasing the number of iterations or increasing the cost of production by using costly packaging. We have explored various ways of reducing leakage power in the design and recommended one, the multi-Vt approach. We have carried out analysis using multi-Vt approach over a test design on 130nm and 90nm technology. We have also highlighted on ways of how and where to apply this approach effectively in a typical ASIC design flow. We compare our results with all other approaches and demonstrate an average reduction in leakage power by almost 4.9 times compared to normal approaches without paying any penalty for speed or even area.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115648580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Generic modeling of nonplanar dielectrics for 2 1/2D parasitic extraction 非平面介质2 1/2D寄生提取的通用建模
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.68
N. Kurt-Karsilayan
{"title":"Generic modeling of nonplanar dielectrics for 2 1/2D parasitic extraction","authors":"N. Kurt-Karsilayan","doi":"10.1109/IWSOC.2005.68","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.68","url":null,"abstract":"Generic modeling of nonplanar dielectrics for 2 1/2D parasitic extraction is addressed. First, basic nonplanar dielectric geometry types are defined. Then it is shown that modeling complex shapes can be simplified based on the overlapping rules for most field solvers. Finally, a novel algorithm based on the overlapping assumption is introduced and the accuracy impact of modeling nonplanar dielectrics is shown based on a realistic technology. This approach is already productized and verified against various technologies along with a 2 1/2D extraction tool.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121277283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A field-programmable analog array using translinear elements 一种使用跨线元件的现场可编程模拟阵列
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.8
David N. Abramson, J. Gray, Shyam Subramanian, P. Hasler
{"title":"A field-programmable analog array using translinear elements","authors":"David N. Abramson, J. Gray, Shyam Subramanian, P. Hasler","doi":"10.1109/IWSOC.2005.8","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.8","url":null,"abstract":"A field programmable analog array that uses translinear elements for computation is introduced. The system uses floating-gate transistors to implement switch networks and MITEs to create reconfigurable translinear networks. The system architecture includes 3 MITE CABs, 1 specialized CAB for implementing four quadrant and dynamic functions, and a global switch matrix used to connect them. A squaring circuit, a square root circuit, a 2nd-order translinear loop, a vector magnitude circuit, and a 1st-order log-domain filter are programmed onto the device and results are presented in order to demonstrate the reconfigurability of the system.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"5 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114108075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Four-valued memory circuit designed by multiple-peak MOS-NDR devices and circuits 采用多峰MOS-NDR器件和电路设计四值存储电路
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.66
Dong-Shong Liang, K. Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Y. Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang
{"title":"Four-valued memory circuit designed by multiple-peak MOS-NDR devices and circuits","authors":"Dong-Shong Liang, K. Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Y. Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang","doi":"10.1109/IWSOC.2005.66","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.66","url":null,"abstract":"This paper describes the design of a four-valued memory cell based on a three-peak MOS-NDR circuit. We connect three MOS-NDR devices in parallel that can create a three-peak current-voltage curve by suitably arranging the parameters. Due to its folding I-V characteristics, multiple-peak NDR device is a very promising device for multiple-valued logic application. This memory cell structure can be easily extended to implement more states in a memory circuit.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123412534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
HW/SW co-design for SoC on mobile platforms 移动平台SoC硬件/软件协同设计
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI: 10.1109/IWSOC.2005.73
J. D. V. Tang, H. Rumpt, D. Kasperkovitz
{"title":"HW/SW co-design for SoC on mobile platforms","authors":"J. D. V. Tang, H. Rumpt, D. Kasperkovitz","doi":"10.1109/IWSOC.2005.73","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.73","url":null,"abstract":"Portable platforms like cell phones, PDAs, and notebooks get more and more feature-packed every year. Given the very short life-cycles of these products, the set-maker has to be able to add additional selling-features like for example FM/AM radio, TV, and wireless links with a minimum of risk, board space, minimum power consumption and cost onto it's already existing product platform. Systems on chip (SoC) in their truest sense, having no external components, and that are optimized for flexibility and low power consumption is the solution to this challenge. This paper discusses the key features and key circuits of the first \"no-external components\" FM radio and TV tuners for mobile platforms. Both SoCs make use of resources that are generally available on mobile platforms like a reference clock and a microprocessor. The signal processing path of both ICs is fully controlled by software and adaptable as a result of hardware/software co-design. For the set-maker, both ICs can be virtually treated as digital ICs as there are no \"hot\" RF components off-chip, nor is any other component off-chip. RF building blocks like a broadband tunable LNA (on the TV IC) and an I/Q oscillator (on the FM IC and TV IC) are discussed in detail.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123674621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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